From 3dc7b719a6530e19fa1bdefb5e75423c14268d8b Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 9 Mar 2018 13:35:37 +0000
Subject: [PATCH]

---
 shakti/m_class/wishbone.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/shakti/m_class/wishbone.mdwn b/shakti/m_class/wishbone.mdwn
index e623b71fd..6748b9f8e 100644
--- a/shakti/m_class/wishbone.mdwn
+++ b/shakti/m_class/wishbone.mdwn
@@ -1,5 +1,7 @@
 # Wishbone Bridge
 
 See also [[AXI]] Bus
+
 * <http://bugs.libre-riscv.org/show_bug.cgi?id=11>
 * <https://github.com/alexforencich/verilog-wishbone>
+* <https://github.com/albertxie/iverilog-tutorial.git>
-- 
2.30.2