From 402f120ea8c0e7d5f474528b5905151beb0851f6 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 May 2019 06:08:21 +0100
Subject: [PATCH] move code around to get set associative cache working

---
 src/TLB/SetAssociativeCache.py             | 10 ++++------
 src/TLB/ariane/__init__.py                 |  0
 src/TLB/ariane/{src => }/exceptcause.py    |  0
 src/TLB/ariane/{src => }/mmu.py            |  0
 src/TLB/ariane/{src => }/plru.py           |  4 ++--
 src/TLB/ariane/{src => }/ptw.py            |  0
 src/TLB/ariane/{src => }/tlb.py            |  0
 src/TLB/ariane/{src => }/tlb_content.py    |  0
 src/TLB/test/test_set_associative_cache.py | 17 ++++++++---------
 9 files changed, 14 insertions(+), 17 deletions(-)
 create mode 100644 src/TLB/ariane/__init__.py
 rename src/TLB/ariane/{src => }/exceptcause.py (100%)
 rename src/TLB/ariane/{src => }/mmu.py (100%)
 rename src/TLB/ariane/{src => }/plru.py (98%)
 rename src/TLB/ariane/{src => }/ptw.py (100%)
 rename src/TLB/ariane/{src => }/tlb.py (100%)
 rename src/TLB/ariane/{src => }/tlb_content.py (100%)

diff --git a/src/TLB/SetAssociativeCache.py b/src/TLB/SetAssociativeCache.py
index 0acd3488..70c075da 100644
--- a/src/TLB/SetAssociativeCache.py
+++ b/src/TLB/SetAssociativeCache.py
@@ -6,22 +6,20 @@ http://www.ntu.edu.sg/home/smitha/ParaCache/Paracache/sa4.html
 Python simulator of a N-way set-associative cache:
 https://github.com/vaskevich/CacheSim/blob/master/cachesim.py
 """
-import sys
-sys.path.append("ariane/src/")
 
 from nmigen import Array, Cat, Memory, Module, Signal, Mux, Elaboratable
 from nmigen.compat.genlib import fsm
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 
-from AddressEncoder import AddressEncoder
-from MemorySet import MemorySet
+from .AddressEncoder import AddressEncoder
+from .MemorySet import MemorySet
 
 # TODO: use a LFSR that advances continuously and picking the bottom
 # few bits from it to select which cache line to replace, instead of PLRU
 # http://bugs.libre-riscv.org/show_bug.cgi?id=71
-from plru import PLRU
-from LFSR import LFSR, LFSR_POLY_24
+from .ariane.plru import PLRU
+from .LFSR import LFSR, LFSR_POLY_24
 
 SA_NA = "00" # no action (none)
 SA_RD = "01" # read
diff --git a/src/TLB/ariane/__init__.py b/src/TLB/ariane/__init__.py
new file mode 100644
index 00000000..e69de29b
diff --git a/src/TLB/ariane/src/exceptcause.py b/src/TLB/ariane/exceptcause.py
similarity index 100%
rename from src/TLB/ariane/src/exceptcause.py
rename to src/TLB/ariane/exceptcause.py
diff --git a/src/TLB/ariane/src/mmu.py b/src/TLB/ariane/mmu.py
similarity index 100%
rename from src/TLB/ariane/src/mmu.py
rename to src/TLB/ariane/mmu.py
diff --git a/src/TLB/ariane/src/plru.py b/src/TLB/ariane/plru.py
similarity index 98%
rename from src/TLB/ariane/src/plru.py
rename to src/TLB/ariane/plru.py
index 95d515c4..c82ec01a 100644
--- a/src/TLB/ariane/src/plru.py
+++ b/src/TLB/ariane/plru.py
@@ -2,7 +2,7 @@ from nmigen import Signal, Module, Cat, Const
 from nmigen.hdl.ir import Elaboratable
 from math import log2
 
-from ptw import TLBUpdate, PTE, ASID_WIDTH
+from .ptw import TLBUpdate, PTE, ASID_WIDTH
 
 class PLRU(Elaboratable):
     """ PLRU - Pseudo Least Recently Used Replacement
@@ -103,4 +103,4 @@ class PLRU(Elaboratable):
 
     def ports(self):
         return [self.entries, self.lu_hit, self.replace_en_o,
-                self.lu_access_i, self.plru_tree, self.plru_tree_o]
\ No newline at end of file
+                self.lu_access_i, self.plru_tree, self.plru_tree_o]
diff --git a/src/TLB/ariane/src/ptw.py b/src/TLB/ariane/ptw.py
similarity index 100%
rename from src/TLB/ariane/src/ptw.py
rename to src/TLB/ariane/ptw.py
diff --git a/src/TLB/ariane/src/tlb.py b/src/TLB/ariane/tlb.py
similarity index 100%
rename from src/TLB/ariane/src/tlb.py
rename to src/TLB/ariane/tlb.py
diff --git a/src/TLB/ariane/src/tlb_content.py b/src/TLB/ariane/tlb_content.py
similarity index 100%
rename from src/TLB/ariane/src/tlb_content.py
rename to src/TLB/ariane/tlb_content.py
diff --git a/src/TLB/test/test_set_associative_cache.py b/src/TLB/test/test_set_associative_cache.py
index d681425f..0641b556 100644
--- a/src/TLB/test/test_set_associative_cache.py
+++ b/src/TLB/test/test_set_associative_cache.py
@@ -1,12 +1,8 @@
-import sys
-sys.path.append("../src")
-sys.path.append("../../TestUtil")
-
 from nmigen.compat.sim import run_simulation
 
-from SetAssociativeCache import SetAssociativeCache
+from TLB.SetAssociativeCache import SetAssociativeCache
 
-from test_helper import assert_eq, assert_ne, assert_op
+from TestUtil.test_helper import assert_eq, assert_ne, assert_op
 
 def set_sac(dut, e, c, s, t, d):
     yield dut.enable.eq(e)
@@ -16,7 +12,7 @@ def set_sac(dut, e, c, s, t, d):
     yield dut.data_i.eq(d)
     yield
 
-def testbench(dut):
+def tbench(dut):
     enable = 1
     command = 2
     cset = 1
@@ -33,7 +29,10 @@ def testbench(dut):
     yield from set_sac(dut, enable, command, cset, tag, data)
     yield
 
-if __name__ == "__main__":
+def test_assoc_cache():
     dut = SetAssociativeCache(4, 4, 4, 4)
-    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_set_associative_cache.vcd")
+    run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_set_associative_cache.vcd")
     print("Set Associative Cache Unit Test Success")
+
+if __name__ == "__main__":
+    test_assoc_cache()
-- 
2.30.2