From 41d2c31f6f0d184a57f468d5b157d6e8c0a44af1 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Sun, 13 Dec 2020 15:03:59 -0300 Subject: [PATCH] Allow more test cases to be run with CXXSim --- src/soc/decoder/test/test_decoder_gas.py | 6 +++++- src/soc/experiment/dcache.py | 9 +++++---- src/soc/experiment/icache.py | 8 ++++---- src/soc/experiment/mmu.py | 8 ++++---- 4 files changed, 18 insertions(+), 13 deletions(-) diff --git a/src/soc/decoder/test/test_decoder_gas.py b/src/soc/decoder/test/test_decoder_gas.py index 72d05a79..f65abfac 100644 --- a/src/soc/decoder/test/test_decoder_gas.py +++ b/src/soc/decoder/test/test_decoder_gas.py @@ -1,5 +1,9 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Delay + from nmutil.formaltest import FHDLTestCase import unittest from soc.decoder.power_decoder import (create_pdecode) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 732e9f3a..e1f82b77 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -33,10 +33,11 @@ from nmutil.plru import PLRU from nmigen_soc.wishbone.sram import SRAM from nmigen import Memory from nmigen.cli import rtlil -if True: - from nmigen.back.pysim import Simulator, Delay, Settle -else: - from nmigen.sim.cxxsim import Simulator, Delay, Settle + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator + from nmutil.util import wrap diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index 06031af0..fb01baf4 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -45,10 +45,10 @@ from nmigen_soc.wishbone.sram import SRAM from nmigen import Memory from nmutil.util import wrap from nmigen.cli import main, rtlil -if True: - from nmigen.back.pysim import Simulator, Delay, Settle -else: - from nmigen.sim.cxxsim import Simulator, Delay, Settle + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle SIM = 0 diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py index a8c514f7..8e63bdec 100644 --- a/src/soc/experiment/mmu.py +++ b/src/soc/experiment/mmu.py @@ -20,10 +20,10 @@ from nmutil.byterev import byte_reverse from nmutil.mask import Mask, masked from nmutil.util import Display -if True: - from nmigen.back.pysim import Simulator, Delay, Settle -else: - from nmigen.sim.cxxsim import Simulator, Delay, Settle +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle + from nmutil.util import wrap from soc.experiment.mem_types import (LoadStore1ToMMUType, -- 2.30.2