From 42f7357660b245c4491297d24eebc28b4ac2c21f Mon Sep 17 00:00:00 2001 From: Las Safin Date: Sat, 25 Sep 2021 15:49:30 +0000 Subject: [PATCH] versa_ecp5.py: Fix csr_address_width --- versa_ecp5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/versa_ecp5.py b/versa_ecp5.py index 18aca0e..a8f2455 100755 --- a/versa_ecp5.py +++ b/versa_ecp5.py @@ -29,7 +29,7 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC): kwargs["integrated_rom_size"] = 0x10000 #kwargs["integrated_main_ram_size"] = 0x1000 kwargs["csr_data_width"] = 32 - kwargs['csr_address_width'] = 12 # limit to 0x8000 + kwargs['csr_address_width'] = 15 # limit to 0x8000 kwargs["l2_size"] = 0 #bus_data_width = 16, -- 2.30.2