From 43635b424591c7b7a36e910b85b6af5ef762047b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 28 Jun 2019 08:46:31 +0100 Subject: [PATCH] add comments on parameters --- src/ieee754/fpcommon/roundz.py | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py index db4482b6..36253d37 100644 --- a/src/ieee754/fpcommon/roundz.py +++ b/src/ieee754/fpcommon/roundz.py @@ -14,9 +14,10 @@ class FPRoundData: def __init__(self, width, id_wid): self.z = FPNumBaseRecord(width, False) + self.mid = Signal(id_wid, reset_less=True) # multiplex ID + # pipeline bypass [data comes from specialcases] self.out_do_z = Signal(reset_less=True) self.oz = Signal(width, reset_less=True) - self.mid = Signal(id_wid, reset_less=True) def eq(self, i): return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz), @@ -47,7 +48,7 @@ class FPRoundMod(Elaboratable): def elaborate(self, platform): m = Module() m.d.comb += self.out_z.eq(self.i) # copies mid, z, out_do_z - with m.If(~self.i.out_do_z): + with m.If(~self.i.out_do_z): # bypass wasn't enabled with m.If(self.i.roundz): m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up with m.If(self.i.z.m == self.i.z.m1s): # all 1s -- 2.30.2