From 451f50d7b920e63683d2b9a40e88fef8c3056bd7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 14 Jan 2024 20:11:57 +0000 Subject: [PATCH] bug 676: nearly there. just <= vs < to deal with --- src/openpower/decoder/isa/test_caller_svp64_maxloc.py | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py index 831472cf..151984de 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py +++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py @@ -55,7 +55,7 @@ class DDFFirstTestCase(FHDLTestCase): self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64)) def test_sv_maxloc_1(self): - self.sv_maxloc([2,3,0,7]) + self.sv_maxloc([9,10,11,10]) def tst_sv_maxloc_2(self): self.sv_maxloc([3,4,1,5]) @@ -92,13 +92,10 @@ class DDFFirstTestCase(FHDLTestCase): #"sv.addi/mr/sm=ge/dm=ns 4, *4, 0", # r4 = last non-masked value "mtcrf 128, 0", # clear CR0 (in case VL=0?) "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # uses r4 as accumulator + "sv.svstep/mr/m=ge 3, 0, 6, 1", # svstep: get vector dststep "sv.creqv *16,*16,*16", # set mask on already-tested - "sv.crand *19,*16,0", # set mask on less-than - "sv.cror *19,*19,2", # and equal - "sv.svstep/mr/m=so 3, 0, 6, 1", # svstep: get vector dststep - "add 1,1,3", # accumulate dststep #"sv.addi/dm=1<r4 (and dec CTR) ]) -- 2.30.2