From 45435ce4bc4d2a8946a51725c7b804c8160bc91f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 16 Apr 2022 21:23:38 +0100 Subject: [PATCH] put versa_ecp5 back to synchronous at 50 mhz to test sync dram --- src/ls2.py | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/ls2.py b/src/ls2.py index ec81aa3..38110d0 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -856,8 +856,8 @@ def build_platform(fpga, firmware): #dram_clk_freq = clk_freq dram_clk_freq = 100e6 if fpga == 'versa_ecp5': - clk_freq = 40e6 # crank right down to timing threshold - dram_clk_freq = 55e6 + clk_freq = 50e6 # crank right down to timing threshold + #dram_clk_freq = 55e6 if fpga == 'versa_ecp5_85': # 50MHz works. 100MHz works. 55MHz does NOT work. # Stick with multiples of 50MHz... @@ -874,6 +874,13 @@ def build_platform(fpga, firmware): if clk_freq == dram_clk_freq: dram_clk_freq = None + # see if dram can be enabled + enable_dram = False + if dram_clk_freq is not None and dram_clk_freq >= 50e6: + enable_dram = True + if dram_clk_freq is None and clk_freq >= 50e6: + enable_dram = True + # select a firmware address fw_addr = None if firmware is not None: @@ -894,7 +901,7 @@ def build_platform(fpga, firmware): # get DDR resource pins, disable if clock frequency is below 50 mhz for now ddr_pins = None - if (dram_clk_freq >= 50e6 and platform is not None and + if (enable_dram and platform is not None and fpga in ['versa_ecp5', 'versa_ecp5_85', 'arty_a7', 'isim']): ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"}, -- 2.30.2