From 4944ab3c0296f906549d7eb3417fbaa771e476fe Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Wed, 24 Apr 2013 01:46:16 -0700 Subject: [PATCH] fixes to correctly simulate the vector unit --- README | 2 +- riscv/decode.h | 2 ++ riscv/processor.cc | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/README b/README index 0a1ff90..5ba221d 100644 --- a/README +++ b/README @@ -1,7 +1,7 @@ ========================================================================== RISC-V ISA Simulator ========================================================================== -# Author : Andrew Waterman +# Author : Andrew Waterman, Yunsup Lee # Date : June 19, 2011 # Version : (under version control) diff --git a/riscv/decode.h b/riscv/decode.h index bf16e72..3ef8864 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -152,6 +152,8 @@ public: } write_port_t write_port(size_t i) { + if (zero_reg) + const_cast(data[0]) = 0; return write_port_t(data[i]); } const T& operator [] (size_t i) const diff --git a/riscv/processor.cc b/riscv/processor.cc index 39a9ec0..e124820 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -299,6 +299,8 @@ reg_t processor_t::get_pcr(int which) return pcr_k1; case PCR_VECBANK: return vecbanks; + case PCR_VECCFG: + return nfpr_use << 18 | nxpr_use << 12 | vl; case PCR_TOHOST: return tohost; case PCR_FROMHOST: -- 2.30.2