From 4bcd977ea2c22f5d5eb0c5b7e74c8e76d3d3d007 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Jul 2019 09:11:42 +0100 Subject: [PATCH] more imports / syntax errors --- src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 7 ++++--- src/ieee754/fpdiv/divstages.py | 6 +++++- src/ieee754/fpdiv/specialcases.py | 2 +- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 2facb95a..2c6ec33a 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -89,6 +89,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData): def eq(self, rhs): """ Assign member signals. """ + print (self, rhs) return DivPipeCoreInterstageData.eq(self, rhs) + \ DivPipeBaseData.eq(self, rhs) @@ -131,8 +132,8 @@ class DivPipeBaseStage: class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage): def __init__(self, pspec): - DivPipeCoreSetupStage.__init__(self.get_core_config()) self.pspec = pspec + DivPipeCoreSetupStage.__init__(self, pspec.core_config) def elaborate(self, platform): m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic! @@ -143,8 +144,8 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage): class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage): def __init__(self, pspec, stage_index): - DivPipeCoreCalculateStage.__init__(self.get_core_config(), stage_index) self.pspec = pspec + DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index) def elaborate(self, platform): m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! @@ -155,8 +156,8 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage): class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage): def __init__(self, pspec, stage_index): - DivPipeCoreFinalStage.__init__(self.get_core_config(), stage_index) self.pspec = pspec + DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index) def elaborate(self, platform): m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic! diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py index 1b41b9e7..914e7723 100644 --- a/src/ieee754/fpdiv/divstages.py +++ b/src/ieee754/fpdiv/divstages.py @@ -12,7 +12,11 @@ from nmutil.singlepipe import (StageChain, SimpleHandshake) from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.postcalc import FPAddStage1Data -from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInterstageData +from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData, + DivPipeSetupStage, + DivPipeCalculateStage, + DivPipeFinalStage, + ) # TODO: write these from .div0 import FPDivStage0Mod diff --git a/src/ieee754/fpdiv/specialcases.py b/src/ieee754/fpdiv/specialcases.py index d039eaaf..4a73e435 100644 --- a/src/ieee754/fpdiv/specialcases.py +++ b/src/ieee754/fpdiv/specialcases.py @@ -101,7 +101,7 @@ class FPDIVSpecialCasesMod(Elaboratable): m.d.comb += self.o.out_do_z.eq(0) m.d.comb += self.o.oz.eq(self.o.z.v) - m.d.comb += self.o.mid.eq(self.i.mid) + m.d.comb += self.o.ctx.eq(self.i.ctx) return m -- 2.30.2