From 525523d0a0a1aa84eebac97c474563e3f1dae459 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 31 May 2018 17:05:47 +0100 Subject: [PATCH] add RGB565 example --- simple_v_extension/simple_v_chennai_2018.tex | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 498ed9fae..79f4a699a 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -277,15 +277,16 @@ for (int i = 0; i < VL; ++i) \frame{\frametitle{Why are overlaps allowed in Regfiles?} \begin{itemize} - \item Same register(s) can have multiple "interpretations"\vspace{10pt} - \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{10pt} - \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{10pt} - \item Same register(s) can be offset (no need for VSLIDE)\vspace{10pt} + \item Same register(s) can have multiple "interpretations"\vspace{6pt} + \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{6pt} + \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV)\vspace{6pt} + \item RGB 565 (video): BEXTW plus 4x8-bit SIMD plus BDEPW\vspace{6pt} + \item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt} \end{itemize} Note:\vspace{10pt} \begin{itemize} - \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$) \vspace{10pt} - \item Hi-Performance: Macro-op fusion (more pipeline stages?)\vspace{10pt} + \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$) + \item Hi-Performance: Macro-op fusion (more pipeline stages?) \end{itemize} } -- 2.30.2