From 541b7fc509914f8a68b9b7245c6b77987caf396a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 26 May 2021 14:07:13 +0000 Subject: [PATCH] remove sram4k wb err (unused anyway) --- .../full_core_4_4ksram_libresoc.v | 2134 ++++++++--------- .../full_core_4_4ksram_litex_ls180.v | 64 +- 2 files changed, 1093 insertions(+), 1105 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_libresoc.v b/experiments9/non_generated/full_core_4_4ksram_libresoc.v index 17b2605..ae0adce 100644 --- a/experiments9/non_generated/full_core_4_4ksram_libresoc.v +++ b/experiments9/non_generated/full_core_4_4ksram_libresoc.v @@ -22850,9 +22850,9 @@ module adr_l(coresync_rst, s_adr, r_adr, q_adr, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_adr; @@ -22912,9 +22912,9 @@ module adrok_l(coresync_rst, s_addr_acked, r_addr_acked, qn_addr_acked, q_addr_a wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_addr_acked; @@ -23349,9 +23349,9 @@ module alu0(coresync_rst, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -24652,9 +24652,9 @@ module alu_alu0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, n_ input alu_op__zero_a; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \alu_op__zero_a$71 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -25816,9 +25816,9 @@ module alu_branch0(coresync_rst, fast1_ok, fast2_ok, nia_ok, n_valid_o, n_ready_ (* enum_value_10 = "UNSIGNED" *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \br_op__sv_saturate$29 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; @@ -26201,9 +26201,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.cr0.alu_cr0" *) (* generator = "nMigen" *) module alu_cr0(coresync_rst, o_ok, full_cr_ok, cr_a_ok, n_valid_o, n_ready_i, cr_op__insn_type, cr_op__fn_unit, cr_op__insn, cr_op__sv_pred_sz, cr_op__sv_pred_dz, cr_op__sv_saturate, cr_op__SV_Ptype, o, full_cr, cr_a, ra, rb, \full_cr$1 , \cr_a$2 , cr_b, cr_c, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -26804,9 +26804,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.div0.alu_div0" *) (* generator = "nMigen" *) module alu_div0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -28466,9 +28466,9 @@ module alu_l(coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28528,9 +28528,9 @@ module \alu_l$107 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28590,9 +28590,9 @@ module \alu_l$125 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28652,9 +28652,9 @@ module \alu_l$128 (coresync_rst, s_alu, r_alu, q_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28714,9 +28714,9 @@ module \alu_l$16 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28776,9 +28776,9 @@ module \alu_l$29 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28838,9 +28838,9 @@ module \alu_l$45 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28900,9 +28900,9 @@ module \alu_l$61 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -28962,9 +28962,9 @@ module \alu_l$73 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -29024,9 +29024,9 @@ module \alu_l$90 (coresync_rst, q_alu, r_alu, s_alu, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alu; @@ -29069,9 +29069,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.logical0.alu_logical0" *) (* generator = "nMigen" *) module alu_logical0(coresync_rst, o_ok, cr_a_ok, n_valid_o, n_ready_i, logical_op__insn_type, logical_op__fn_unit, logical_op__imm_data__data, logical_op__imm_data__ok, logical_op__rc__rc, logical_op__rc__ok, logical_op__oe__oe, logical_op__oe__ok, logical_op__invert_in, logical_op__zero_a, logical_op__input_carry, logical_op__invert_out, logical_op__write_cr0, logical_op__output_carry, logical_op__is_32bit, logical_op__is_signed, logical_op__data_len, logical_op__insn, logical_op__sv_pred_sz, logical_op__sv_pred_dz, logical_op__sv_saturate, logical_op__SV_Ptype, o, cr_a, ra, rb, xer_so, p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -30216,9 +30216,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.mul0.alu_mul0" *) (* generator = "nMigen" *) module alu_mul0(coresync_rst, o_ok, cr_a_ok, xer_ov_ok, xer_so_ok, n_valid_o, n_ready_i, mul_op__insn_type, mul_op__fn_unit, mul_op__imm_data__data, mul_op__imm_data__ok, mul_op__rc__rc, mul_op__rc__ok, mul_op__oe__oe, mul_op__oe__ok, mul_op__write_cr0, mul_op__is_32bit, mul_op__is_signed, mul_op__insn, mul_op__sv_pred_sz, mul_op__sv_pred_dz, mul_op__sv_saturate, mul_op__SV_Ptype, o, cr_a, xer_ov, xer_so, ra, rb, \xer_so$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -31613,9 +31613,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" *) (* generator = "nMigen" *) module alu_shift_rot0(coresync_rst, o_ok, cr_a_ok, xer_ca_ok, n_valid_o, n_ready_i, sr_op__insn_type, sr_op__fn_unit, sr_op__imm_data__data, sr_op__imm_data__ok, sr_op__rc__rc, sr_op__rc__ok, sr_op__oe__oe, sr_op__oe__ok, sr_op__write_cr0, sr_op__invert_in, sr_op__input_carry, sr_op__output_carry, sr_op__input_cr, sr_op__output_cr, sr_op__is_32bit, sr_op__is_signed, sr_op__insn, sr_op__sv_pred_sz, sr_op__sv_pred_dz, sr_op__sv_saturate, sr_op__SV_Ptype, o, cr_a, xer_ca, ra, rb, rc, xer_so, \xer_ca$1 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -32780,9 +32780,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.spr0.alu_spr0" *) (* generator = "nMigen" *) module alu_spr0(coresync_rst, o_ok, xer_ca_ok, xer_ov_ok, xer_so_ok, fast1_ok, spr1_ok, n_valid_o, n_ready_i, spr_op__insn_type, spr_op__fn_unit, spr_op__insn, spr_op__is_32bit, spr_op__sv_pred_sz, spr_op__sv_pred_dz, spr_op__sv_saturate, spr_op__SV_Ptype, o, spr1, fast1, xer_so, xer_ov, xer_ca, ra, \spr1$1 , \fast1$2 , \xer_so$3 , \xer_ov$4 , \xer_ca$5 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast1; @@ -33426,9 +33426,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus.trap0.alu_trap0" *) (* generator = "nMigen" *) module alu_trap0(coresync_rst, o_ok, fast1_ok, fast2_ok, fast3_ok, nia_ok, msr_ok, svstate_ok, n_valid_o, n_ready_i, trap_op__insn_type, trap_op__fn_unit, trap_op__insn, trap_op__msr, trap_op__cia, trap_op__svstate, trap_op__is_32bit, trap_op__traptype, trap_op__trapaddr, trap_op__ldst_exc, trap_op__sv_pred_sz, trap_op__sv_pred_dz, trap_op__sv_saturate, trap_op__SV_Ptype, o, fast1, fast2, fast3, nia, msr, svstate, ra, rb, \fast1$1 , \fast2$2 , \fast3$3 , p_valid_i, p_ready_o, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [63:0] fast1; @@ -34501,9 +34501,9 @@ module alui_l(coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34563,9 +34563,9 @@ module \alui_l$106 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34625,9 +34625,9 @@ module \alui_l$124 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34687,9 +34687,9 @@ module \alui_l$15 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34749,9 +34749,9 @@ module \alui_l$28 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34811,9 +34811,9 @@ module \alui_l$44 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34873,9 +34873,9 @@ module \alui_l$60 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34935,9 +34935,9 @@ module \alui_l$72 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -34997,9 +34997,9 @@ module \alui_l$89 (coresync_rst, q_alui, r_alui, s_alui, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_alui; @@ -36720,9 +36720,9 @@ module branch0(coresync_rst, oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_t reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -37536,9 +37536,9 @@ module busy_l(coresync_rst, s_busy, r_busy, q_busy, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_busy; @@ -41369,9 +41369,9 @@ module core(coresync_rst, corebusy_o, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, c (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *) output corebusy_o; reg corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:215" *) reg [1:0] counter = 2'h0; @@ -54083,9 +54083,9 @@ module cr(coresync_rst, full_rd2__ren, full_rd2__data_o, full_rd__data_o, full_r wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] data_i; @@ -54979,9 +54979,9 @@ module cr0(coresync_rst, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, ope reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -55805,9 +55805,9 @@ module cyc_l(coresync_rst, s_cyc, r_cyc, q_cyc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_cyc; @@ -55976,7 +55976,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c wire \$97 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" *) wire \$99 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) input [6:0] core_dbg_core_dbg_dststep; @@ -56079,7 +56079,7 @@ module dbg(rst, dmi_addr_i, dmi_req_i, dmi_we_i, dmi_din, dmi_ack_o, dmi_dout, c wire [63:0] log_dmi_data; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" *) wire [31:0] log_write_addr_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" *) wire [63:0] stat_reg; @@ -141541,9 +141541,9 @@ module div0(coresync_rst, oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -142868,9 +142868,9 @@ endmodule (* generator = "nMigen" *) module fast(coresync_rst, issue__addr, issue__ren, issue__data_o, \issue__addr$1 , issue__wen, issue__data_i, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest1__addr; @@ -143333,9 +143333,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.fus" *) (* generator = "nMigen" *) module fus(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, exc_o_happened, oper_i_alu_alu0__insn_type, oper_i_alu_alu0__fn_unit, oper_i_alu_alu0__imm_data__data, oper_i_alu_alu0__imm_data__ok, oper_i_alu_alu0__rc__rc, oper_i_alu_alu0__rc__ok, oper_i_alu_alu0__oe__oe, oper_i_alu_alu0__oe__ok, oper_i_alu_alu0__invert_in, oper_i_alu_alu0__zero_a, oper_i_alu_alu0__invert_out, oper_i_alu_alu0__write_cr0, oper_i_alu_alu0__input_carry, oper_i_alu_alu0__output_carry, oper_i_alu_alu0__is_32bit, oper_i_alu_alu0__is_signed, oper_i_alu_alu0__data_len, oper_i_alu_alu0__insn, oper_i_alu_alu0__sv_pred_sz, oper_i_alu_alu0__sv_pred_dz, oper_i_alu_alu0__sv_saturate, oper_i_alu_alu0__SV_Ptype, cu_issue_i, cu_busy_o, cu_rdmaskn_i, oper_i_alu_cr0__insn_type, oper_i_alu_cr0__fn_unit, oper_i_alu_cr0__insn, oper_i_alu_cr0__sv_pred_sz, oper_i_alu_cr0__sv_pred_dz, oper_i_alu_cr0__sv_saturate, oper_i_alu_cr0__SV_Ptype, \cu_issue_i$1 , \cu_busy_o$2 , \cu_rdmaskn_i$3 , oper_i_alu_branch0__cia, oper_i_alu_branch0__insn_type, oper_i_alu_branch0__fn_unit, oper_i_alu_branch0__insn, oper_i_alu_branch0__imm_data__data, oper_i_alu_branch0__imm_data__ok, oper_i_alu_branch0__lk, oper_i_alu_branch0__is_32bit, oper_i_alu_branch0__sv_pred_sz, oper_i_alu_branch0__sv_pred_dz, oper_i_alu_branch0__sv_saturate, oper_i_alu_branch0__SV_Ptype, \cu_issue_i$4 , \cu_busy_o$5 , \cu_rdmaskn_i$6 , oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_unit, oper_i_alu_trap0__insn, oper_i_alu_trap0__msr, oper_i_alu_trap0__cia, oper_i_alu_trap0__svstate, oper_i_alu_trap0__is_32bit, oper_i_alu_trap0__traptype, oper_i_alu_trap0__trapaddr, oper_i_alu_trap0__ldst_exc, oper_i_alu_trap0__sv_pred_sz, oper_i_alu_trap0__sv_pred_dz, oper_i_alu_trap0__sv_saturate, oper_i_alu_trap0__SV_Ptype, \cu_issue_i$7 , \cu_busy_o$8 , \cu_rdmaskn_i$9 , oper_i_alu_logical0__insn_type, oper_i_alu_logical0__fn_unit, oper_i_alu_logical0__imm_data__data, oper_i_alu_logical0__imm_data__ok, oper_i_alu_logical0__rc__rc, oper_i_alu_logical0__rc__ok, oper_i_alu_logical0__oe__oe, oper_i_alu_logical0__oe__ok, oper_i_alu_logical0__invert_in, oper_i_alu_logical0__zero_a, oper_i_alu_logical0__input_carry, oper_i_alu_logical0__invert_out, oper_i_alu_logical0__write_cr0, oper_i_alu_logical0__output_carry, oper_i_alu_logical0__is_32bit, oper_i_alu_logical0__is_signed, oper_i_alu_logical0__data_len, oper_i_alu_logical0__insn, oper_i_alu_logical0__sv_pred_sz, oper_i_alu_logical0__sv_pred_dz, oper_i_alu_logical0__sv_saturate, oper_i_alu_logical0__SV_Ptype, \cu_issue_i$10 , \cu_busy_o$11 , \cu_rdmaskn_i$12 , oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, oper_i_alu_spr0__insn, oper_i_alu_spr0__is_32bit, oper_i_alu_spr0__sv_pred_sz, oper_i_alu_spr0__sv_pred_dz, oper_i_alu_spr0__sv_saturate, oper_i_alu_spr0__SV_Ptype, \cu_issue_i$13 , \cu_busy_o$14 , \cu_rdmaskn_i$15 , oper_i_alu_div0__insn_type, oper_i_alu_div0__fn_unit, oper_i_alu_div0__imm_data__data, oper_i_alu_div0__imm_data__ok, oper_i_alu_div0__rc__rc, oper_i_alu_div0__rc__ok, oper_i_alu_div0__oe__oe, oper_i_alu_div0__oe__ok, oper_i_alu_div0__invert_in, oper_i_alu_div0__zero_a, oper_i_alu_div0__input_carry, oper_i_alu_div0__invert_out, oper_i_alu_div0__write_cr0, oper_i_alu_div0__output_carry, oper_i_alu_div0__is_32bit, oper_i_alu_div0__is_signed, oper_i_alu_div0__data_len, oper_i_alu_div0__insn, oper_i_alu_div0__sv_pred_sz, oper_i_alu_div0__sv_pred_dz, oper_i_alu_div0__sv_saturate, oper_i_alu_div0__SV_Ptype, \cu_issue_i$16 , \cu_busy_o$17 , \cu_rdmaskn_i$18 , oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, oper_i_alu_mul0__imm_data__data, oper_i_alu_mul0__imm_data__ok, oper_i_alu_mul0__rc__rc, oper_i_alu_mul0__rc__ok, oper_i_alu_mul0__oe__oe, oper_i_alu_mul0__oe__ok, oper_i_alu_mul0__write_cr0, oper_i_alu_mul0__is_32bit, oper_i_alu_mul0__is_signed, oper_i_alu_mul0__insn, oper_i_alu_mul0__sv_pred_sz, oper_i_alu_mul0__sv_pred_dz, oper_i_alu_mul0__sv_saturate, oper_i_alu_mul0__SV_Ptype, \cu_issue_i$19 , \cu_busy_o$20 , \cu_rdmaskn_i$21 , oper_i_alu_shift_rot0__insn_type, oper_i_alu_shift_rot0__fn_unit, oper_i_alu_shift_rot0__imm_data__data, oper_i_alu_shift_rot0__imm_data__ok, oper_i_alu_shift_rot0__rc__rc, oper_i_alu_shift_rot0__rc__ok, oper_i_alu_shift_rot0__oe__oe, oper_i_alu_shift_rot0__oe__ok, oper_i_alu_shift_rot0__write_cr0, oper_i_alu_shift_rot0__invert_in, oper_i_alu_shift_rot0__input_carry, oper_i_alu_shift_rot0__output_carry, oper_i_alu_shift_rot0__input_cr, oper_i_alu_shift_rot0__output_cr, oper_i_alu_shift_rot0__is_32bit, oper_i_alu_shift_rot0__is_signed, oper_i_alu_shift_rot0__insn, oper_i_alu_shift_rot0__sv_pred_sz, oper_i_alu_shift_rot0__sv_pred_dz, oper_i_alu_shift_rot0__sv_saturate, oper_i_alu_shift_rot0__SV_Ptype, \cu_issue_i$22 , \cu_busy_o$23 , \cu_rdmaskn_i$24 , oper_i_ldst_ldst0__insn_type, oper_i_ldst_ldst0__fn_unit, oper_i_ldst_ldst0__imm_data__data, oper_i_ldst_ldst0__imm_data__ok, oper_i_ldst_ldst0__zero_a, oper_i_ldst_ldst0__rc__rc, oper_i_ldst_ldst0__rc__ok, oper_i_ldst_ldst0__oe__oe, oper_i_ldst_ldst0__oe__ok, oper_i_ldst_ldst0__msr, oper_i_ldst_ldst0__is_32bit, oper_i_ldst_ldst0__is_signed, oper_i_ldst_ldst0__data_len, oper_i_ldst_ldst0__byte_reverse, oper_i_ldst_ldst0__sign_extend, oper_i_ldst_ldst0__ldst_mode, oper_i_ldst_ldst0__insn, oper_i_ldst_ldst0__sv_pred_sz, oper_i_ldst_ldst0__sv_pred_dz, oper_i_ldst_ldst0__sv_saturate, oper_i_ldst_ldst0__SV_Ptype, \cu_issue_i$25 , \cu_busy_o$26 , \cu_rdmaskn_i$27 , cu_rd__rel_o, cu_rd__go_i, src2_i, \cu_rd__rel_o$28 , \cu_rd__go_i$29 , \src2_i$30 , \cu_rd__rel_o$31 , \cu_rd__go_i$32 , \src2_i$33 , \cu_rd__rel_o$34 , \cu_rd__go_i$35 , \src2_i$36 , \cu_rd__rel_o$37 , \cu_rd__go_i$38 , \src2_i$39 , \cu_rd__rel_o$40 , \cu_rd__go_i$41 , \src2_i$42 , \cu_rd__rel_o$43 , \cu_rd__go_i$44 , \src2_i$45 , \cu_rd__rel_o$46 , \cu_rd__go_i$47 , \src2_i$48 , src3_i, \src3_i$49 , src1_i, \src1_i$50 , \src1_i$51 , \src1_i$52 , \cu_rd__rel_o$53 , \cu_rd__go_i$54 , \src1_i$55 , \src1_i$56 , \src1_i$57 , \src1_i$58 , \src1_i$59 , \src3_i$60 , \src3_i$61 , src4_i, \src3_i$62 , \src3_i$63 , \src4_i$64 , \src4_i$65 , src6_i, src5_i, \src5_i$66 , \src3_i$67 , \src4_i$68 , \cu_rd__rel_o$69 , \cu_rd__go_i$70 , \src3_i$71 , \src5_i$72 , \src6_i$73 , \src1_i$74 , \src3_i$75 , \src3_i$76 , \src2_i$77 , \src4_i$78 , \src5_i$79 , \src2_i$80 , o_ok, cu_wr__rel_o, cu_wr__go_i, \o_ok$81 , \cu_wr__rel_o$82 , \cu_wr__go_i$83 , \o_ok$84 , \cu_wr__rel_o$85 , \cu_wr__go_i$86 , \o_ok$87 , \cu_wr__rel_o$88 , \cu_wr__go_i$89 , \o_ok$90 , \cu_wr__rel_o$91 , \cu_wr__go_i$92 , \o_ok$93 , \cu_wr__rel_o$94 , \cu_wr__go_i$95 , \o_ok$96 , \cu_wr__rel_o$97 , \cu_wr__go_i$98 , \o_ok$99 , \cu_wr__rel_o$100 , \cu_wr__go_i$101 , \cu_wr__rel_o$102 , \cu_wr__go_i$103 , dest1_o, \dest1_o$104 , \dest1_o$105 , \dest1_o$106 , \dest1_o$107 , \dest1_o$108 , \dest1_o$109 , \dest1_o$110 , o, ea, full_cr_ok, dest2_o, cr_a_ok, \cr_a_ok$111 , \cr_a_ok$112 , \cr_a_ok$113 , \cr_a_ok$114 , \cr_a_ok$115 , \dest2_o$116 , dest3_o, \dest2_o$117 , \dest2_o$118 , \dest2_o$119 , \dest2_o$120 , xer_ca_ok, \xer_ca_ok$121 , \xer_ca_ok$122 , \dest3_o$123 , dest6_o, \dest3_o$124 , xer_ov_ok, \xer_ov_ok$125 , \xer_ov_ok$126 , \xer_ov_ok$127 , dest4_o, dest5_o, \dest3_o$128 , \dest3_o$129 , xer_so_ok, \xer_so_ok$130 , \xer_so_ok$131 , \xer_so_ok$132 , \dest5_o$133 , \dest4_o$134 , \dest4_o$135 , \dest4_o$136 , fast1_ok, \cu_wr__rel_o$137 , \cu_wr__go_i$138 , \fast1_ok$139 , \fast1_ok$140 , fast2_ok, \fast2_ok$141 , fast3_ok, \dest1_o$142 , \dest2_o$143 , \dest3_o$144 , \dest2_o$145 , \dest3_o$146 , \dest4_o$147 , nia_ok, \nia_ok$148 , \dest3_o$149 , \dest5_o$150 , msr_ok, \dest6_o$151 , svstate_ok, dest7_o, spr1_ok, \dest2_o$152 , ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -145638,9 +145638,9 @@ module idx_l(coresync_rst, q_idx_l, s_idx_l, r_idx_l, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) output q_idx_l; @@ -145744,7 +145744,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en wire a_stall_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" *) input a_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" *) reg [44:0] f_badaddr_o = 45'h000000000000; @@ -145794,7 +145794,7 @@ module imem(rst, a_pc_i, a_valid_i, f_valid_i, f_busy_o, f_instr_o, wb_icache_en reg [63:0] ibus_rdata = 64'h0000000000000000; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" *) reg [63:0] \ibus_rdata$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) input wb_icache_en; @@ -147913,9 +147913,9 @@ endmodule (* generator = "nMigen" *) module \int (coresync_rst, dmi__addr, dmi__ren, dmi__data_o, src1__data_o, src1__addr, src1__ren, dest1__data_i, dest1__addr, dest1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [4:0] dest1__addr; @@ -148639,7 +148639,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, input TAP_bus__tms; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:420" *) reg TAP_tdo; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) input dmi0__ack_o; @@ -149087,7 +149087,7 @@ module jtag(rst, dmi0__addr_i, dmi0__req_i, dmi0__we_i, dmi0__din, dmi0__ack_o, wire posjtag_clk; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" *) wire posjtag_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -150746,9 +150746,9 @@ endmodule (* \nmigen.hierarchy = "test_issuer.ti.core.l0" *) (* generator = "nMigen" *) module l0(coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_data_len, ldst_port0_addr_i, ldst_port0_addr_i_ok, ldst_port0_exc_alignment, ldst_port0_exc_instr_fault, ldst_port0_exc_invalid, ldst_port0_exc_badtree, ldst_port0_exc_perm_error, ldst_port0_exc_rc_error, ldst_port0_exc_segment_fault, ldst_port0_exc_happened, ldst_port0_addr_ok_o, ldst_port0_msr_pr, ldst_port0_ld_data_o, ldst_port0_ld_data_o_ok, ldst_port0_st_data_i, ldst_port0_st_data_i_ok, wb_dcache_en, dbus__cyc, dbus__ack, dbus__err, dbus__stb, dbus__sel, dbus__dat_r, dbus__adr, dbus__we, dbus__dat_w, coresync_clk); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -150957,9 +150957,9 @@ module \l0$130 (coresync_rst, ldst_port0_busy_o, ldst_port0_is_ld_i, ldst_port0_ wire [95:0] \$26 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:138" *) wire [95:0] \$27 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" *) reg \idx_l$16 = 1'h0; @@ -151415,9 +151415,9 @@ module ld_active(coresync_rst, r_ld_active, s_ld_active, q_ld_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -151679,9 +151679,9 @@ module ldst0(coresync_rst, cu_st__rel_o, cu_ad__go_i, cu_ad__rel_o, cu_st__go_i, wire alu_valid; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452" *) wire cancel; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" *) input cu_ad__go_i; @@ -153548,9 +153548,9 @@ module lod_l(coresync_rst, s_lod, r_lod, qn_lod, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -153957,9 +153957,9 @@ module logical0(coresync_rst, oper_i_alu_logical0__insn_type, oper_i_alu_logical reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -154782,9 +154782,9 @@ module logical_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -156350,9 +156350,9 @@ module logical_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$57 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; @@ -157528,9 +157528,9 @@ module lsd_l(coresync_rst, s_lsd, r_lsd, q_lsd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -157670,9 +157670,9 @@ module lsmem(coresync_rst, x_mask_i, x_addr_i, m_ld_data_o, x_st_data_i, x_busy_ wire \$93 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" *) wire \$95 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -163414,9 +163414,9 @@ module mul0(coresync_rst, oper_i_alu_mul0__insn_type, oper_i_alu_mul0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -165430,9 +165430,9 @@ module mul_pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) @@ -166824,9 +166824,9 @@ module mul_pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* enum_base_type = "SVPtype" *) (* enum_value_00 = "NONE" *) @@ -167875,9 +167875,9 @@ module mul_pipe3(coresync_rst, p_valid_i, p_ready_o, muxid, mul_op__insn_type, m reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -169752,9 +169752,9 @@ module opc_l(coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -169814,9 +169814,9 @@ module \opc_l$102 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -169876,9 +169876,9 @@ module \opc_l$11 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -169938,9 +169938,9 @@ module \opc_l$120 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170000,9 +170000,9 @@ module \opc_l$126 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170062,9 +170062,9 @@ module \opc_l$24 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170124,9 +170124,9 @@ module \opc_l$40 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170186,9 +170186,9 @@ module \opc_l$56 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170248,9 +170248,9 @@ module \opc_l$68 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -170310,9 +170310,9 @@ module \opc_l$85 (coresync_rst, s_opc, r_opc, q_opc, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -173716,9 +173716,9 @@ module pimem(coresync_rst, ldst_port0_is_ld_i, ldst_port0_is_st_i, ldst_port0_bu reg busy_l_r_busy; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) reg busy_l_s_busy; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" *) wire cyc_l_q_cyc; @@ -174432,9 +174432,9 @@ module pipe(coresync_rst, p_valid_i, p_ready_o, muxid, cr_op__insn_type, cr_op__ reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; @@ -175754,9 +175754,9 @@ module \pipe$19 (coresync_rst, p_valid_i, p_ready_o, muxid, br_op__cia, br_op__i (* enum_value_10 = "UNSIGNED" *) (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire [1:0] \br_op__sv_saturate$45 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [3:0] cr_a; @@ -176334,9 +176334,9 @@ module \pipe$64 (coresync_rst, p_valid_i, p_ready_o, muxid, spr_op__insn_type, s reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$30 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; @@ -177908,9 +177908,9 @@ module pipe1(coresync_rst, n_valid_o, n_ready_i, muxid, alu_op__insn_type, alu_o wire \alu_op__zero_a$91 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) reg \alu_op__zero_a$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -179064,9 +179064,9 @@ module \pipe1$110 (coresync_rst, n_valid_o, n_ready_i, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$77 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -180677,9 +180677,9 @@ module \pipe1$32 (coresync_rst, n_valid_o, n_ready_i, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) wire [63:0] dummy_fast1; @@ -182219,9 +182219,9 @@ module pipe2(coresync_rst, p_valid_i, p_ready_o, muxid, alu_op__insn_type, alu_o reg \alu_op__zero_a$11$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:22" *) wire \alu_op__zero_a$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; @@ -183022,9 +183022,9 @@ module \pipe2$115 (coresync_rst, p_valid_i, p_ready_o, muxid, sr_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$59 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [3:0] cr_a; @@ -184222,9 +184222,9 @@ module \pipe2$35 (coresync_rst, p_valid_i, p_ready_o, muxid, trap_op__insn_type, reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$38 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:31" *) input [63:0] fast1; @@ -185428,9 +185428,9 @@ module pipe_end(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn_type reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output [3:0] cr_a; @@ -187118,9 +187118,9 @@ module pipe_middle_0(coresync_rst, p_valid_i, p_ready_o, muxid, logical_op__insn wire \$71 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) input div_by_zero; @@ -188180,9 +188180,9 @@ module pipe_start(coresync_rst, n_valid_o, n_ready_i, muxid, logical_op__insn_ty reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" *) wire \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" *) output div_by_zero; @@ -191262,9 +191262,9 @@ module reg_0(coresync_rst, src10__ren, src10__data_o, src20__ren, src20__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest10__data_i; @@ -191735,9 +191735,9 @@ module \reg_0$132 (coresync_rst, src10__ren, src10__data_o, src20__ren, src20__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest10__data_i; @@ -192189,9 +192189,9 @@ module \reg_0$135 (coresync_rst, cia0__ren, cia0__data_o, msr0__ren, msr0__data_ reg [63:0] \cia0__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia0__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr10__data_i; @@ -192585,9 +192585,9 @@ module reg_1(coresync_rst, src11__ren, src11__data_o, src21__ren, src21__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest11__data_i; @@ -193058,9 +193058,9 @@ module \reg_1$133 (coresync_rst, src11__ren, src11__data_o, src21__ren, src21__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest11__data_i; @@ -193512,9 +193512,9 @@ module \reg_1$136 (coresync_rst, cia1__ren, cia1__data_o, msr1__ren, msr1__data_ reg [63:0] \cia1__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia1__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr11__data_i; @@ -193908,9 +193908,9 @@ module reg_2(coresync_rst, src12__ren, src12__data_o, src22__ren, src22__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest12__data_i; @@ -194381,9 +194381,9 @@ module \reg_2$134 (coresync_rst, src12__ren, src12__data_o, src22__ren, src22__d wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] dest12__data_i; @@ -194835,9 +194835,9 @@ module \reg_2$137 (coresync_rst, cia2__ren, cia2__data_o, msr2__ren, msr2__data_ reg [63:0] \cia2__data_o$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input cia2__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] d_wr12__data_i; @@ -195231,9 +195231,9 @@ module reg_3(coresync_rst, src13__ren, src13__data_o, src23__ren, src23__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest13__data_i; @@ -195706,9 +195706,9 @@ module reg_4(coresync_rst, src14__ren, src14__data_o, src24__ren, src24__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest14__data_i; @@ -196181,9 +196181,9 @@ module reg_5(coresync_rst, src15__ren, src15__data_o, src25__ren, src25__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest15__data_i; @@ -196656,9 +196656,9 @@ module reg_6(coresync_rst, src16__ren, src16__data_o, src26__ren, src26__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest16__data_i; @@ -197131,9 +197131,9 @@ module reg_7(coresync_rst, src17__ren, src17__data_o, src27__ren, src27__data_o, wire \$6 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [3:0] dest17__data_i; @@ -197612,9 +197612,9 @@ module req_l(coresync_rst, q_req, s_req, r_req, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -197674,9 +197674,9 @@ module \req_l$103 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -197736,9 +197736,9 @@ module \req_l$12 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -197798,9 +197798,9 @@ module \req_l$121 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -197860,9 +197860,9 @@ module \req_l$25 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -197922,9 +197922,9 @@ module \req_l$41 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [6:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [6:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [6:0] q_int = 7'h00; @@ -197984,9 +197984,9 @@ module \req_l$57 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [1:0] q_int = 2'h0; @@ -198046,9 +198046,9 @@ module \req_l$69 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -198108,9 +198108,9 @@ module \req_l$86 (coresync_rst, q_req, s_req, r_req, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -198164,9 +198164,9 @@ module reset_l(coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -198217,9 +198217,9 @@ module \reset_l$131 (coresync_rst, s_reset, r_reset, q_reset, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -198867,9 +198867,9 @@ module rok_l(coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -198929,9 +198929,9 @@ module \rok_l$105 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -198991,9 +198991,9 @@ module \rok_l$123 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199053,9 +199053,9 @@ module \rok_l$14 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199115,9 +199115,9 @@ module \rok_l$27 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199177,9 +199177,9 @@ module \rok_l$43 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199239,9 +199239,9 @@ module \rok_l$59 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199301,9 +199301,9 @@ module \rok_l$71 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199363,9 +199363,9 @@ module \rok_l$88 (coresync_rst, q_rdok, s_rdok, r_rdok, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199815,9 +199815,9 @@ module rst_l(coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199877,9 +199877,9 @@ module \rst_l$104 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -199939,9 +199939,9 @@ module \rst_l$122 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200001,9 +200001,9 @@ module \rst_l$129 (coresync_rst, s_rst, r_rst, q_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200063,9 +200063,9 @@ module \rst_l$13 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200125,9 +200125,9 @@ module \rst_l$26 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200187,9 +200187,9 @@ module \rst_l$42 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200249,9 +200249,9 @@ module \rst_l$58 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200311,9 +200311,9 @@ module \rst_l$70 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -200373,9 +200373,9 @@ module \rst_l$87 (coresync_rst, s_rst, r_rst, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -201240,9 +201240,9 @@ module shiftrot0(coresync_rst, oper_i_alu_shift_rot0__insn_type, oper_i_alu_shif reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) output cr_a_ok; @@ -202144,9 +202144,9 @@ endmodule (* generator = "nMigen" *) module spr(coresync_rst, spr1__data_o, spr1__addr, spr1__ren, spr1__data_i, \spr1__addr$1 , spr1__wen, coresync_clk); reg \initial = 0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:211" *) wire [3:0] memory_r_addr; @@ -202561,9 +202561,9 @@ module spr0(coresync_rst, oper_i_alu_spr0__insn_type, oper_i_alu_spr0__fn_unit, reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -207058,7 +207058,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac wire \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) reg [63:0] d; @@ -207066,7 +207066,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac input enable; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) output sram4k_0_wb__ack; @@ -207202,7 +207202,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac wire \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) reg [63:0] d; @@ -207210,7 +207210,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac input enable; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) output sram4k_1_wb__ack; @@ -207346,7 +207346,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac wire \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) reg [63:0] d; @@ -207354,7 +207354,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac input enable; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) output sram4k_2_wb__ack; @@ -207490,7 +207490,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac wire \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:44" *) reg [8:0] a; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:47" *) reg [63:0] d; @@ -207498,7 +207498,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac input enable; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:46" *) wire [63:0] q; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) output sram4k_3_wb__ack; @@ -207646,9 +207646,9 @@ module src_l(coresync_rst, s_src, r_src, q_src, coresync_clk); wire [3:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [3:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [3:0] q_int = 4'h0; @@ -207708,9 +207708,9 @@ module \src_l$10 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -207770,9 +207770,9 @@ module \src_l$101 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -207832,9 +207832,9 @@ module \src_l$119 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -207894,9 +207894,9 @@ module \src_l$127 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -207956,9 +207956,9 @@ module \src_l$23 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -208018,9 +208018,9 @@ module \src_l$39 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [4:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [4:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [4:0] q_int = 5'h00; @@ -208080,9 +208080,9 @@ module \src_l$55 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -208142,9 +208142,9 @@ module \src_l$67 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [5:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [5:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [5:0] q_int = 6'h00; @@ -208204,9 +208204,9 @@ module \src_l$84 (coresync_rst, s_src, r_src, q_src, coresync_clk); wire [2:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire [2:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg [2:0] q_int = 3'h0; @@ -208266,9 +208266,9 @@ module st_active(coresync_rst, r_st_active, s_st_active, q_st_active, coresync_c wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -208328,9 +208328,9 @@ module st_done(coresync_rst, s_st_done, r_st_done, q_st_done, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -208397,9 +208397,9 @@ module state(coresync_rst, cia__ren, cia__data_o, sv__ren, sv__data_o, wen, data reg [63:0] cia__data_o; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [2:0] cia__ren; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [63:0] data_i; @@ -208716,9 +208716,9 @@ module sto_l(coresync_rst, s_sto, r_sto, q_sto, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -208761,8 +208761,8 @@ endmodule (* \nmigen.hierarchy = "test_issuer" *) (* top = 1 *) (* generator = "nMigen" *) -module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_0_wb__err, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_1_wb__err, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_2_wb__err, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, sram4k_3_wb__err, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i); - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *) +module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__tdo, TAP_bus__tdi, TAP_bus__tms, TAP_bus__tck, jtag_wb__adr, jtag_wb__dat_w, jtag_wb__dat_r, jtag_wb__sel, jtag_wb__cyc, jtag_wb__stb, jtag_wb__we, jtag_wb__ack, jtag_wb__err, mspi0_clk__core__o, mspi0_clk__pad__o, mspi0_cs_n__core__o, mspi0_cs_n__pad__o, mspi0_mosi__core__o, mspi0_mosi__pad__o, mspi0_miso__core__i, mspi0_miso__pad__i, sdr_dm_0__core__o, sdr_dm_0__pad__o, sdr_dq_0__core__i, sdr_dq_0__core__o, sdr_dq_0__core__oe, sdr_dq_0__pad__i, sdr_dq_0__pad__o, sdr_dq_0__pad__oe, sdr_dq_1__core__i, sdr_dq_1__core__o, sdr_dq_1__core__oe, sdr_dq_1__pad__i, sdr_dq_1__pad__o, sdr_dq_1__pad__oe, sdr_dq_2__core__i, sdr_dq_2__core__o, sdr_dq_2__core__oe, sdr_dq_2__pad__i, sdr_dq_2__pad__o, sdr_dq_2__pad__oe, sdr_dq_3__core__i, sdr_dq_3__core__o, sdr_dq_3__core__oe, sdr_dq_3__pad__i, sdr_dq_3__pad__o, sdr_dq_3__pad__oe, sdr_dq_4__core__i, sdr_dq_4__core__o, sdr_dq_4__core__oe, sdr_dq_4__pad__i, sdr_dq_4__pad__o, sdr_dq_4__pad__oe, sdr_dq_5__core__i, sdr_dq_5__core__o, sdr_dq_5__core__oe, sdr_dq_5__pad__i, sdr_dq_5__pad__o, sdr_dq_5__pad__oe, sdr_dq_6__core__i, sdr_dq_6__core__o, sdr_dq_6__core__oe, sdr_dq_6__pad__i, sdr_dq_6__pad__o, sdr_dq_6__pad__oe, sdr_dq_7__core__i, sdr_dq_7__core__o, sdr_dq_7__core__oe, sdr_dq_7__pad__i, sdr_dq_7__pad__o, sdr_dq_7__pad__oe, sdr_a_0__core__o, sdr_a_0__pad__o, sdr_a_1__core__o, sdr_a_1__pad__o, sdr_a_2__core__o, sdr_a_2__pad__o, sdr_a_3__core__o, sdr_a_3__pad__o, sdr_a_4__core__o, sdr_a_4__pad__o, sdr_a_5__core__o, sdr_a_5__pad__o, sdr_a_6__core__o, sdr_a_6__pad__o, sdr_a_7__core__o, sdr_a_7__pad__o, sdr_a_8__core__o, sdr_a_8__pad__o, sdr_a_9__core__o, sdr_a_9__pad__o, sdr_ba_0__core__o, sdr_ba_0__pad__o, sdr_ba_1__core__o, sdr_ba_1__pad__o, sdr_clock__core__o, sdr_clock__pad__o, sdr_cke__core__o, sdr_cke__pad__o, sdr_ras_n__core__o, sdr_ras_n__pad__o, sdr_cas_n__core__o, sdr_cas_n__pad__o, sdr_we_n__core__o, sdr_we_n__pad__o, sdr_cs_n__core__o, sdr_cs_n__pad__o, sdr_a_10__core__o, sdr_a_10__pad__o, sdr_a_11__core__o, sdr_a_11__pad__o, sdr_a_12__core__o, sdr_a_12__pad__o, sdr_dm_1__core__o, sdr_dm_1__pad__o, sdr_dq_8__core__i, sdr_dq_8__core__o, sdr_dq_8__core__oe, sdr_dq_8__pad__i, sdr_dq_8__pad__o, sdr_dq_8__pad__oe, sdr_dq_9__core__i, sdr_dq_9__core__o, sdr_dq_9__core__oe, sdr_dq_9__pad__i, sdr_dq_9__pad__o, sdr_dq_9__pad__oe, sdr_dq_10__core__i, sdr_dq_10__core__o, sdr_dq_10__core__oe, sdr_dq_10__pad__i, sdr_dq_10__pad__o, sdr_dq_10__pad__oe, sdr_dq_11__core__i, sdr_dq_11__core__o, sdr_dq_11__core__oe, sdr_dq_11__pad__i, sdr_dq_11__pad__o, sdr_dq_11__pad__oe, sdr_dq_12__core__i, sdr_dq_12__core__o, sdr_dq_12__core__oe, sdr_dq_12__pad__i, sdr_dq_12__pad__o, sdr_dq_12__pad__oe, sdr_dq_13__core__i, sdr_dq_13__core__o, sdr_dq_13__core__oe, sdr_dq_13__pad__i, sdr_dq_13__pad__o, sdr_dq_13__pad__oe, sdr_dq_14__core__i, sdr_dq_14__core__o, sdr_dq_14__core__oe, sdr_dq_14__pad__i, sdr_dq_14__pad__o, sdr_dq_14__pad__oe, sdr_dq_15__core__i, sdr_dq_15__core__o, sdr_dq_15__core__oe, sdr_dq_15__pad__i, sdr_dq_15__pad__o, sdr_dq_15__pad__oe, gpio_e8__core__i, gpio_e8__core__o, gpio_e8__core__oe, gpio_e8__pad__i, gpio_e8__pad__o, gpio_e8__pad__oe, gpio_e9__core__i, gpio_e9__core__o, gpio_e9__core__oe, gpio_e9__pad__i, gpio_e9__pad__o, gpio_e9__pad__oe, gpio_e10__core__i, gpio_e10__core__o, gpio_e10__core__oe, gpio_e10__pad__i, gpio_e10__pad__o, gpio_e10__pad__oe, gpio_e11__core__i, gpio_e11__core__o, gpio_e11__core__oe, gpio_e11__pad__i, gpio_e11__pad__o, gpio_e11__pad__oe, gpio_e12__core__i, gpio_e12__core__o, gpio_e12__core__oe, gpio_e12__pad__i, gpio_e12__pad__o, gpio_e12__pad__oe, gpio_e13__core__i, gpio_e13__core__o, gpio_e13__core__oe, gpio_e13__pad__i, gpio_e13__pad__o, gpio_e13__pad__oe, gpio_e14__core__i, gpio_e14__core__o, gpio_e14__core__oe, gpio_e14__pad__i, gpio_e14__pad__o, gpio_e14__pad__oe, gpio_e15__core__i, gpio_e15__core__o, gpio_e15__core__oe, gpio_e15__pad__i, gpio_e15__pad__o, gpio_e15__pad__oe, gpio_s0__core__i, gpio_s0__core__o, gpio_s0__core__oe, gpio_s0__pad__i, gpio_s0__pad__o, gpio_s0__pad__oe, gpio_s1__core__i, gpio_s1__core__o, gpio_s1__core__oe, gpio_s1__pad__i, gpio_s1__pad__o, gpio_s1__pad__oe, gpio_s2__core__i, gpio_s2__core__o, gpio_s2__core__oe, gpio_s2__pad__i, gpio_s2__pad__o, gpio_s2__pad__oe, gpio_s3__core__i, gpio_s3__core__o, gpio_s3__core__oe, gpio_s3__pad__i, gpio_s3__pad__o, gpio_s3__pad__oe, gpio_s4__core__i, gpio_s4__core__o, gpio_s4__core__oe, gpio_s4__pad__i, gpio_s4__pad__o, gpio_s4__pad__oe, gpio_s5__core__i, gpio_s5__core__o, gpio_s5__core__oe, gpio_s5__pad__i, gpio_s5__pad__o, gpio_s5__pad__oe, gpio_s6__core__i, gpio_s6__core__o, gpio_s6__core__oe, gpio_s6__pad__i, gpio_s6__pad__o, gpio_s6__pad__oe, gpio_s7__core__i, gpio_s7__core__o, gpio_s7__core__oe, gpio_s7__pad__i, gpio_s7__pad__o, gpio_s7__pad__oe, mtwi_sda__core__i, mtwi_sda__core__o, mtwi_sda__core__oe, mtwi_sda__pad__i, mtwi_sda__pad__o, mtwi_sda__pad__oe, mtwi_scl__core__o, mtwi_scl__pad__o, eint_0__core__i, eint_0__pad__i, eint_1__core__i, eint_1__pad__i, eint_2__core__i, eint_2__pad__i, ibus__adr, ibus__dat_w, ibus__dat_r, ibus__sel, ibus__cyc, ibus__stb, ibus__ack, ibus__we, ibus__err, ibus__cti, ibus__bte, dbus__adr, dbus__dat_w, dbus__dat_r, dbus__sel, dbus__cyc, dbus__stb, dbus__ack, dbus__we, dbus__err, dbus__cti, dbus__bte, sram4k_0_wb__adr, sram4k_0_wb__dat_w, sram4k_0_wb__dat_r, sram4k_0_wb__sel, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__we, sram4k_0_wb__ack, sram4k_1_wb__adr, sram4k_1_wb__dat_w, sram4k_1_wb__dat_r, sram4k_1_wb__sel, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__we, sram4k_1_wb__ack, sram4k_2_wb__adr, sram4k_2_wb__dat_w, sram4k_2_wb__dat_r, sram4k_2_wb__sel, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__we, sram4k_2_wb__ack, sram4k_3_wb__adr, sram4k_3_wb__dat_w, sram4k_3_wb__dat_r, sram4k_3_wb__sel, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__we, sram4k_3_wb__ack, icp_wb__adr, icp_wb__dat_w, icp_wb__dat_r, icp_wb__sel, icp_wb__cyc, icp_wb__stb, icp_wb__ack, icp_wb__we, icp_wb__err, ics_wb__adr, ics_wb__dat_w, ics_wb__dat_r, ics_wb__sel, ics_wb__cyc, ics_wb__stb, ics_wb__ack, ics_wb__we, ics_wb__err, int_level_i, clk, rst, clk_sel_i, pll_test_o, pll_vco_o, pc_i); + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *) wire [1:0] \$1 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -208772,13 +208772,13 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *) input clk_sel_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) input core_bigendian_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" *) input dbus__ack; @@ -209084,7 +209084,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t output jtag_wb__stb; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:749" *) output jtag_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:242" *) input memerr_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mspi0_clk__core__o; @@ -209122,17 +209122,17 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t input [63:0] pc_i; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *) output [63:0] pc_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1235" *) - output pll_test_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1236" *) + output pll_test_o; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *) output pll_vco_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1252" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *) wire pllclk_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1252" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1253" *) wire pllclk_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -209429,8 +209429,6 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [63:0] sram4k_0_wb__dat_w; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) - input sram4k_0_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [7:0] sram4k_0_wb__sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_0_wb__stb; @@ -209447,8 +209445,6 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [63:0] sram4k_1_wb__dat_w; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) - input sram4k_1_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [7:0] sram4k_1_wb__sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_1_wb__stb; @@ -209465,8 +209461,6 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [63:0] sram4k_2_wb__dat_w; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) - input sram4k_2_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [7:0] sram4k_2_wb__sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_2_wb__stb; @@ -209483,14 +209477,12 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [63:0] sram4k_3_wb__dat_w; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) - input sram4k_3_wb__err; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input [7:0] sram4k_3_wb__sel; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_3_wb__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_3_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) wire ti_coresync_clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" *) wire wrappll_clk_24_i; @@ -209502,7 +209494,7 @@ module test_issuer(pc_i_ok, pc_o, memerr_o, core_bigendian_i, busy_o, TAP_bus__t wire wrappll_pll_test_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:15" *) wire wrappll_pll_vco_o; - assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1237" *) clk_sel_i; + assign \$1 = + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1238" *) clk_sel_i; ti ti ( .TAP_bus__tck(TAP_bus__tck), .TAP_bus__tdi(TAP_bus__tdi), @@ -209871,181 +209863,181 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg \initial = 0; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) wire [6:0] \$101 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$104 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$106 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$108 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) wire \$11 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$110 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$112 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$114 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) wire \$116 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$118 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$120 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) wire [7:0] \$122 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) - wire [7:0] \$123 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) + wire [7:0] \$123 ; + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *) wire [7:0] \$125 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *) wire [7:0] \$126 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) wire \$128 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) wire [2:0] \$13 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$130 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$132 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$134 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$136 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$138 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) wire [2:0] \$14 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$140 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$142 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$144 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *) wire \$146 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$148 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$150 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$152 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) wire \$154 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$156 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$158 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) wire \$16 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$160 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$162 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$164 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$166 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$168 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$170 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$172 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$174 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$176 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$178 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) wire \$18 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$180 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$182 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$184 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *) wire [2:0] \$185 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$188 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$190 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$192 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$194 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$196 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$198 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) wire \$20 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) wire \$200 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$202 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$204 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$206 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$208 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$210 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$212 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$214 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$216 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) wire \$218 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *) wire [2:0] \$219 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$22 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$222 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$224 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) wire \$226 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$228 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$230 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$232 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$234 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$236 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$238 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) wire \$24 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) wire \$240 ; (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) wire [63:0] \$242 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *) wire \$244 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) wire \$246 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) wire \$248 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] \$250 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) wire [63:0] \$252 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) wire [64:0] \$254 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) wire [64:0] \$255 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) wire [64:0] \$257 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) wire [64:0] \$258 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$26 ; @@ -210065,57 +210057,57 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [63:0] \$40 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) wire \$42 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$44 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$46 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$48 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$50 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$52 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$54 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$56 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$58 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) wire \$60 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$62 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$64 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$66 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$68 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) wire \$70 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$72 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) wire \$74 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$76 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$78 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) wire \$80 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) wire \$82 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$84 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) wire \$86 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) wire \$88 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *) wire [64:0] \$90 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *) wire [64:0] \$91 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$93 ; @@ -210123,9 +210115,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [6:0] \$94 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:57" *) wire [31:0] \$97 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *) wire [64:0] \$98 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *) wire [64:0] \$99 ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tck; @@ -210135,15 +210127,15 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output TAP_bus__tdo; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:67" *) input TAP_bus__tms; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:241" *) output busy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) reg [7:0] core_asmcode = 8'h00; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:104" *) reg [7:0] \core_asmcode$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:239" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:240" *) input core_bigendian_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111" *) reg \core_bigendian_i$3 = 1'h0; @@ -210554,7 +210546,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg [2:0] \core_core_xer_in$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:120" *) wire core_corebusy_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) wire core_coresync_rst; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) reg core_cr_out_ok = 1'h0; @@ -210660,7 +210652,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg core_xer_out = 1'h0; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) reg \core_xer_out$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" *) reg cu_st__rel_o_dly = 1'h0; @@ -210668,17 +210660,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire \cu_st__rel_o_dly$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:61" *) wire cu_st__rel_o_rise; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) reg d_cr_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1112" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1113" *) reg \d_cr_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *) reg d_reg_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1102" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1103" *) reg \d_reg_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *) reg d_xer_delay = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1122" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1123" *) reg \d_xer_delay$next ; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) wire [6:0] dbg_core_dbg_core_dbg_dststep; @@ -211277,9 +211269,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [2:0] dec2_xer_in; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:115" *) wire dec2_xer_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) reg [1:0] delay = 2'h3; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) reg [1:0] \delay$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output eint_0__core__i; @@ -211293,35 +211285,35 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output eint_2__core__i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input eint_2__pad__i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:602" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:603" *) wire exc_happened; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) reg exec_fsm_state = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) reg \exec_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1033" *) reg exec_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1031" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1032" *) reg exec_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1037" *) reg exec_pc_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1035" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1036" *) reg exec_pc_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) reg [1:0] fetch_fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) reg [1:0] \fetch_fsm_state$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1021" *) reg fetch_insn_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1019" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1020" *) reg fetch_insn_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" *) reg fetch_pc_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1015" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" *) reg fetch_pc_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) reg [1:0] fsm_state = 2'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) reg [1:0] \fsm_state$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output gpio_e10__core__i; @@ -211571,17 +211563,17 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg imem_f_valid_i; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" *) wire imem_wb_icache_en; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:269" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:270" *) reg insn_done; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" *) input [15:0] int_level_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:774" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:775" *) reg is_last; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1008" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1009" *) wire is_svp64_mode; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) reg [2:0] issue_fsm_state = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) reg [2:0] \issue_fsm_state$next ; (* src = "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" *) reg jtag_dmi0__ack_o = 1'h0; @@ -211633,9 +211625,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus input mspi0_mosi__core__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mspi0_mosi__pad__o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) reg msr_read = 1'h1; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:291" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:292" *) reg \msr_read$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input mtwi_scl__core__o; @@ -211653,7 +211645,7 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus output mtwi_sda__pad__o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) output mtwi_sda__pad__oe; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1156" *) reg [63:0] new_dec; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:28" *) reg [6:0] new_svstate_dststep; @@ -211667,43 +211659,43 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg [1:0] new_svstate_svstep; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/sv/svstate.py:30" *) reg [6:0] new_svstate_vl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) reg [63:0] new_tb; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) wire [6:0] next_dststep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:592" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:593" *) wire [6:0] next_srcstep; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *) reg [63:0] nia = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:997" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:998" *) reg [63:0] \nia$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] pc; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) reg pc_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:976" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) reg \pc_changed$next ; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input [63:0] pc_i; (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) input pc_i_ok; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:236" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:237" *) output [63:0] pc_o; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg pc_ok_delay = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \pc_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:929" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) wire por_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1025" *) wire pred_insn_ready_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1023" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1024" *) reg pred_insn_valid_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1029" *) reg pred_mask_ready_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1027" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1028" *) wire pred_mask_valid_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:75" *) input sdr_a_0__core__o; @@ -212061,9 +212053,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus input sram4k_3_wb__stb; (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:29" *) input sram4k_3_wb__we; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *) reg sv_changed = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:977" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:978" *) reg \sv_changed$next ; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:64" *) reg [63:0] svstate; @@ -212075,9 +212067,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus reg svstate_ok_delay = 1'h0; (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:65" *) reg \svstate_ok_delay$next ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:934" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:935" *) wire ti_rst; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:585" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:586" *) reg update_svstate; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) wire xics_icp_core_irq_o; @@ -212089,93 +212081,93 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus wire [7:0] xics_ics_icp_o_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" *) wire [3:0] xics_ics_icp_o_src; - assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; - assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:365" *) 3'h4; + assign \$9 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read; + assign \$99 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:366" *) 3'h4; assign \$101 = \$98 [2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$97 = imem_f_instr_o >> \$101 ; - assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$106 ; - assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$112 ; - assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; - assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; - assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) 1'h0; - assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; - assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:594" *) 1'h1; - assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1; - assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:604" *) core_exc_o_happened; - assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$132 ; - assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$138 ; - assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; - assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$142 ; - assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) is_svp64_mode; - assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h1; - assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$150 ; - assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; - assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; - assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; - assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$162 ; - assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) dbg_core_rst_o; - assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$168 ; - assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$174 ; - assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$180 ; - assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) 1'h1; + assign \$104 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$106 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$108 = \$104 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$106 ; + assign \$110 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$112 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$114 = \$110 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$112 ; + assign \$116 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed; + assign \$118 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0; + assign \$11 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) 1'h0; + assign \$120 = \$118 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last; + assign \$123 = dec2_cur_cur_srcstep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:595" *) 1'h1; + assign \$126 = dec2_cur_cur_dststep + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:596" *) 1'h1; + assign \$128 = | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:605" *) core_exc_o_happened; + assign \$130 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$132 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$134 = \$130 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$132 ; + assign \$136 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$138 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$140 = \$136 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$138 ; + assign \$142 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0; + assign \$144 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$142 ; + assign \$146 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *) is_svp64_mode; + assign \$148 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$14 = delay - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" *) 1'h1; + assign \$150 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$152 = \$148 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$150 ; + assign \$154 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed; + assign \$156 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0; + assign \$158 = \$156 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last; + assign \$160 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$162 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$164 = \$160 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$162 ; + assign \$166 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$168 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$16 = 1'h0 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) dbg_core_rst_o; + assign \$170 = \$166 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$168 ; + assign \$172 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$174 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$176 = \$172 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$174 ; + assign \$178 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$180 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$182 = \$178 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$180 ; + assign \$185 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *) 1'h1; assign \$184 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$185 ; - assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) rst; - assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$190 ; - assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$196 ; - assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; - assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; - assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; - assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:942" *) \$18 ; - assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$208 ; - assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$214 ; - assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) 3'h4; + assign \$188 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$18 = \$16 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) rst; + assign \$190 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$192 = \$188 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$190 ; + assign \$194 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$196 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$198 = \$194 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$196 ; + assign \$200 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed; + assign \$202 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0; + assign \$204 = \$202 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last; + assign \$206 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$208 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$20 = delay != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:943" *) \$18 ; + assign \$210 = \$206 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$208 ; + assign \$212 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$214 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$216 = \$212 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$214 ; + assign \$219 = core_state_nia_wen & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *) 3'h4; assign \$218 = | (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" *) \$219 ; - assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; - assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$222 ; - assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; - assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; + assign \$222 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0; + assign \$224 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$222 ; + assign \$226 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o; + assign \$228 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; assign \$22 = ~ (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) cu_st__rel_o_dly; - assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$230 ; - assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$236 ; - assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:776" *) dec2_cur_cur_vl; + assign \$230 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$232 = \$228 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$230 ; + assign \$234 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$236 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$238 = \$234 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$236 ; + assign \$240 = next_srcstep == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:777" *) dec2_cur_cur_vl; assign \$242 = + (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/rec.py:178" *) { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; - assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) 7'h01; - assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; - assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) core_corebusy_o; + assign \$244 = core_core_core_insn_type != (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *) 7'h01; + assign \$246 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o; + assign \$248 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) core_corebusy_o; assign \$24 = core_cu_st__rel_o & (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" *) \$22 ; assign \$250 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd2__data_o; assign \$252 = + (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) core_full_rd__data_o; - assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1157" *) 1'h1; - assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1173" *) 1'h1; + assign \$255 = core_issue__data_o - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1158" *) 1'h1; + assign \$258 = core_issue__data_o + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1174" *) 1'h1; assign \$26 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; assign \$28 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:67" *) pc_i_ok; assign \$30 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; @@ -212185,30 +212177,30 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus assign \$38 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; assign \$40 = + (* src = "/home/lkcl/src/libresoc/openpower-isa/src/openpower/decoder/decode2execute1.py:20" *) svstate_i; assign \$42 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:66" *) core_coresync_rst; - assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$46 ; - assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; - assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$50 ; - assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$56 ; - assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; - assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; - assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; - assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) dbg_core_stop_o; - assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) core_coresync_rst; - assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) \$68 ; - assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) 1'h0; - assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) \$72 ; - assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) dbg_core_stop_o; - assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) core_coresync_rst; - assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) \$78 ; - assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) sv_changed; - assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) 1'h0; - assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" *) is_last; - assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) msr_read; - assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:354" *) 3'h4; + assign \$44 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$46 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$48 = \$44 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$46 ; + assign \$50 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0; + assign \$52 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$50 ; + assign \$54 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$56 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$58 = \$54 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$56 ; + assign \$60 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed; + assign \$62 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0; + assign \$64 = \$62 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last; + assign \$66 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) dbg_core_stop_o; + assign \$68 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) core_coresync_rst; + assign \$70 = \$66 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) \$68 ; + assign \$72 = dec2_cur_cur_vl == (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) 1'h0; + assign \$74 = is_svp64_mode & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) \$72 ; + assign \$76 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) dbg_core_stop_o; + assign \$78 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) core_coresync_rst; + assign \$80 = \$76 & (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) \$78 ; + assign \$82 = pc_changed | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) sv_changed; + assign \$84 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) 1'h0; + assign \$86 = \$84 | (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" *) is_last; + assign \$88 = ~ (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) msr_read; + assign \$91 = dec2_cur_pc + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:355" *) 3'h4; assign \$94 = dec2_cur_pc[2] * (* src = "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:605" *) 6'h20; assign \$93 = imem_f_instr_o >> \$94 ; always @(posedge clk) @@ -213061,9 +213053,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \delay$next = delay; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" *) casez (\$11 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:936" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:937" */ 1'h1: \delay$next = \$13 [1:0]; endcase @@ -213080,30 +213072,30 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_srcstep$next = core_core_srcstep; \core_core_vl$next = core_core_vl; \core_core_maxvl$next = core_core_maxvl; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: { \core_core_maxvl$next , \core_core_vl$next , \core_core_srcstep$next , \core_core_dststep$next , \core_core_subvl$next , \core_core_svstep$next , \core_dec$next , \core_eint$next , \core_core_msr$next , \core_core_pc$next } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep, dec2_cur_dec, dec2_cur_eint, dec2_cur_msr, dec2_cur_pc }; endcase @@ -213127,30 +213119,30 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_raw_insn_i$next = core_raw_insn_i; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: \core_raw_insn_i$next = dec2_raw_opcode_in; endcase @@ -213163,30 +213155,30 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_bigendian_i$3$next = \core_bigendian_i$3 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: \core_bigendian_i$3$next = core_bigendian_i; endcase @@ -213199,34 +213191,34 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end exec_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: exec_insn_valid_i = 1'h1; endcase @@ -213235,42 +213227,42 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end exec_pc_ready_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$232 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: exec_pc_ready_i = 1'h1; endcase @@ -213280,46 +213272,46 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end is_last = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$238 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: is_last = \$240 ; endcase @@ -213329,9 +213321,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_wen$4 = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */ 1'h1: \core_wen$4 = 3'h4; endcase @@ -213339,9 +213331,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \core_data_i$5 = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */ 1'h1: \core_data_i$5 = \$242 ; endcase @@ -213349,10 +213341,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end exec_insn_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: exec_insn_ready_o = 1'h1; endcase @@ -213361,23 +213353,23 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_ivalid_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */ 1'h1: core_ivalid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" *) casez (\$244 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" */ 1'h1: core_ivalid_i = 1'h1; endcase @@ -213386,14 +213378,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_issue_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */ 1'h1: core_issue_i = 1'h1; endcase @@ -213403,27 +213395,27 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \exec_fsm_state$next = exec_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */ 1'h1: \exec_fsm_state$next = 1'h1; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) casez (\$246 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */ 1'h1: \exec_fsm_state$next = 1'h0; endcase @@ -213439,18 +213431,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end exec_pc_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) casez (\$248 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */ 1'h1: exec_pc_valid_o = 1'h1; endcase @@ -213459,9 +213451,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_dmi__addr = 5'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 1'h1: core_dmi__addr = dbg_d_gpr_addr[4:0]; endcase @@ -213469,9 +213461,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_dmi__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" *) casez (dbg_d_gpr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" */ 1'h1: core_dmi__ren = 1'h1; endcase @@ -213488,9 +213480,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_gpr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */ 1'h1: dbg_d_gpr_data = core_dmi__data_o; endcase @@ -213498,9 +213490,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_gpr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" *) casez (d_reg_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1104" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1105" */ 1'h1: dbg_d_gpr_ack = 1'h1; endcase @@ -213508,9 +213500,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_full_rd2__ren = 8'h00; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" *) casez (dbg_d_cr_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1110" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1111" */ 1'h1: core_full_rd2__ren = 8'hff; endcase @@ -213527,9 +213519,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_cr_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */ 1'h1: dbg_d_cr_data = \$250 ; endcase @@ -213537,9 +213529,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_cr_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" *) casez (d_cr_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1114" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1115" */ 1'h1: dbg_d_cr_ack = 1'h1; endcase @@ -213547,9 +213539,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_full_rd__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" *) casez (dbg_d_xer_req) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1120" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1121" */ 1'h1: core_full_rd__ren = 3'h7; endcase @@ -213566,9 +213558,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_xer_data = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */ 1'h1: dbg_d_xer_data = \$252 ; endcase @@ -213576,9 +213568,9 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end dbg_d_xer_ack = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" *) casez (d_xer_delay) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1124" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1125" */ 1'h1: dbg_d_xer_ack = 1'h1; endcase @@ -213586,18 +213578,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_issue__addr = 4'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: core_issue__addr = 4'h6; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: core_issue__addr = 4'h7; endcase @@ -213605,18 +213597,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_issue__ren = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: core_issue__ren = 1'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: core_issue__ren = 1'h1; endcase @@ -213624,22 +213616,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: \fsm_state$next = 2'h1; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: \fsm_state$next = 2'h2; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: \fsm_state$next = 2'h3; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */ 2'h3: \fsm_state$next = 2'h0; endcase @@ -213652,14 +213644,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end new_dec = 64'h0000000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: new_dec = \$254 [63:0]; endcase @@ -213668,22 +213660,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \core_issue__addr$6 = 4'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: \core_issue__addr$6 = 4'h6; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */ 2'h3: \core_issue__addr$6 = 4'h7; endcase @@ -213692,22 +213684,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_issue__wen = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: core_issue__wen = 1'h1; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */ 2'h3: core_issue__wen = 1'h1; endcase @@ -213716,22 +213708,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_issue__data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: core_issue__data_i = new_dec; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */ 2'h3: core_issue__data_i = new_tb; endcase @@ -213740,22 +213732,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end new_tb = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: /* empty */; /* \nmigen.decoding = "TB_READ/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1165" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1166" */ 2'h2: /* empty */; /* \nmigen.decoding = "TB_WRITE/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1171" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1172" */ 2'h3: new_tb = \$257 [63:0]; endcase @@ -213781,20 +213773,20 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \dec2_cur_cur_vl$next = dec2_cur_cur_vl; \dec2_cur_cur_maxvl$next = dec2_cur_cur_maxvl; \dec2_cur_eint$next = xics_icp_core_irq_o; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:971" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:972" */ 1'h1: { \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next , \dec2_cur_dec$next , \dec2_cur_eint$next , \dec2_cur_msr$next , \dec2_cur_pc$next } = 225'h000000000000000000000000000000000000000000000000000000000; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: begin \dec2_cur_pc$next = pc; @@ -213802,29 +213794,29 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) casez (\$9 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */ 1'h1: \dec2_cur_msr$next = core_msr__data_o; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" *) casez (update_svstate) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" */ 1'h1: { \dec2_cur_cur_maxvl$next , \dec2_cur_cur_vl$next , \dec2_cur_cur_srcstep$next , \dec2_cur_cur_dststep$next , \dec2_cur_cur_subvl$next , \dec2_cur_cur_svstep$next } = { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep }; endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1145" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1146" *) casez (fsm_state) /* \nmigen.decoding = "DEC_READ/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1148" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1149" */ 2'h0: /* empty */; /* \nmigen.decoding = "DEC_WRITE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1154" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1155" */ 2'h1: \dec2_cur_dec$next = new_dec; endcase @@ -213972,87 +213964,87 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_wen = 3'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$48 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) casez (\$52 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */ 1'h1: core_wen = 3'h1; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$58 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) casez ({ \$64 , \$60 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ 2'b1?: core_wen = 3'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */ 1'h1: core_wen = 3'h1; endcase @@ -214072,87 +214064,87 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end core_data_i = 64'h0000000000000000; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$70 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 1'h1: core_data_i = pc_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) casez (\$74 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */ 1'h1: core_data_i = nia; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$80 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) casez ({ \$86 , \$82 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ 2'b1?: core_data_i = nia; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */ 1'h1: core_data_i = pc_i; endcase @@ -214162,14 +214154,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end core_msr__ren = 3'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: core_msr__ren = 3'h2; endcase @@ -214187,10 +214179,10 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end fetch_pc_ready_o = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: fetch_pc_ready_o = 1'h1; endcase @@ -214198,14 +214190,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end imem_a_pc_i = 48'h000000000000; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: imem_a_pc_i = pc[47:0]; endcase @@ -214214,32 +214206,32 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end imem_a_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */ 1'h1: imem_a_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */ 1'h1: imem_a_valid_i = 1'h1; endcase @@ -214248,32 +214240,32 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end imem_f_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */ 1'h1: imem_f_valid_i = 1'h1; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 2'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */ 1'h1: imem_f_valid_i = 1'h1; endcase @@ -214282,23 +214274,23 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \msr_read$next = msr_read; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: \msr_read$next = 1'h0; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" *) casez (\$88 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:318" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:319" */ 1'h1: \msr_read$next = 1'h1; endcase @@ -214313,49 +214305,49 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \fetch_fsm_state$next = fetch_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" *) casez (fetch_pc_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:298" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:299" */ 1'h1: \fetch_fsm_state$next = 2'h1; endcase /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */ default: \fetch_fsm_state$next = 2'h2; endcase /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */ 2'h2: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" *) casez (fetch_insn_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:387" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:388" */ 1'h1: \fetch_fsm_state$next = 2'h0; endcase @@ -214369,29 +214361,29 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \nia$next = nia; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */ default: \nia$next = \$90 [63:0]; endcase endcase - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" *) casez (core_coresync_rst) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1070" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1071" */ 1'h1: \nia$next = 64'h0000000000000000; endcase @@ -214404,35 +214396,35 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end \dec2_raw_opcode_in$next = dec2_raw_opcode_in; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:321" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:322" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:325" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:326" */ default: \dec2_raw_opcode_in$next = \$93 ; endcase /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 2'h3: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" *) casez (imem_f_busy_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:363" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:364" */ default: \dec2_raw_opcode_in$next = \$97 ; endcase @@ -214442,22 +214434,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end fetch_insn_valid_o = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:293" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" *) casez (fetch_fsm_state) /* \nmigen.decoding = "IDLE/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:296" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:297" */ 2'h0: /* empty */; /* \nmigen.decoding = "INSN_READ/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:316" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:317" */ 2'h1: /* empty */; /* \nmigen.decoding = "INSN_READ2/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:358" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:359" */ 2'h3: /* empty */; /* \nmigen.decoding = "INSN_READY/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:384" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:385" */ 2'h2: fetch_insn_valid_o = 1'h1; endcase @@ -214466,75 +214458,75 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = { dec2_cur_cur_maxvl, dec2_cur_cur_vl, dec2_cur_cur_srcstep, dec2_cur_cur_dststep, dec2_cur_cur_subvl, dec2_cur_cur_svstep }; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$108 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$114 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) casez ({ \$120 , \$116 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ 2'b1?: begin new_svstate_srcstep = 7'h00; new_svstate_dststep = 7'h00; end - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */ default: begin new_svstate_srcstep = next_srcstep; @@ -214542,11 +214534,11 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus end endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */ 1'h1: { new_svstate_maxvl, new_svstate_vl, new_svstate_srcstep, new_svstate_dststep, new_svstate_subvl, new_svstate_svstep } = svstate_i; endcase @@ -214556,14 +214548,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end fetch_pc_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$134 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: fetch_pc_valid_i = 1'h1; endcase @@ -214573,101 +214565,101 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \issue_fsm_state$next = issue_fsm_state; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$140 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" *) casez (fetch_pc_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:616" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:617" */ 1'h1: \issue_fsm_state$next = 3'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) casez (\$144 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */ 1'h1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:647" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:648" */ default: \issue_fsm_state$next = 3'h2; endcase endcase /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" *) casez (pred_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:655" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:656" */ 1'h1: \issue_fsm_state$next = 3'h4; endcase /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" *) casez (pred_mask_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:660" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:661" */ 1'h1: \issue_fsm_state$next = 3'h5; endcase /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" *) casez (\$146 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" */ 1'h1: \issue_fsm_state$next = 3'h2; endcase /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: \issue_fsm_state$next = 3'h6; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" *) casez (exec_insn_ready_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:749" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:750" */ 1'h1: \issue_fsm_state$next = 3'h7; endcase /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$152 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) casez ({ \$158 , \$154 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 2'b?1: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ 2'b1?: \issue_fsm_state$next = 3'h0; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */ default: \issue_fsm_state$next = 3'h5; endcase @@ -214684,55 +214676,55 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end dbg_core_stopped_i = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$164 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: dbg_core_stopped_i = 1'h1; endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$170 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: dbg_core_stopped_i = 1'h1; endcase @@ -214742,87 +214734,87 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \pc_changed$next = pc_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$176 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:622" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$182 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" *) casez (pc_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:818" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:819" */ 1'h1: \pc_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */ 1'h1: \pc_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" *) casez (\$184 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:874" */ 1'h1: \pc_changed$next = 1'h1; endcase @@ -214837,81 +214829,81 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end update_svstate = 1'h0; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$192 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */ 1'h1: update_svstate = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$198 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" *) casez (exec_pc_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:771" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:772" */ 1'h1: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" *) casez ({ \$204 , \$200 }) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:781" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:782" */ 2'b?1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:788" */ 2'b1?: update_svstate = 1'h1; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:808" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:809" */ default: update_svstate = 1'h1; endcase endcase - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */ 1'h1: update_svstate = 1'h1; endcase @@ -214922,87 +214914,87 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus if (\initial ) begin end \sv_changed$next = sv_changed; (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" *) casez (\$210 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:614" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:615" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:627" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: /* empty */; /* \nmigen.decoding = "INSN_EXECUTE/6" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:747" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:748" */ 3'h6: /* empty */; /* \nmigen.decoding = "EXECUTE_WAIT/7" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:752" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:753" */ 3'h7: (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" *) casez (\$216 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:755" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:756" */ 1'h1: /* empty */; - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:815" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:816" */ default: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" *) casez (svstate_i_ok) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:822" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:823" */ 1'h1: \sv_changed$next = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" *) casez (exec_insn_valid_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:859" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:860" */ 1'h1: \sv_changed$next = 1'h0; endcase /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" *) casez (\$218 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" */ 1'h1: \sv_changed$next = 1'h1; endcase @@ -215016,14 +215008,14 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end fetch_insn_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: fetch_insn_ready_i = 1'h1; endcase @@ -215031,44 +215023,44 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end insn_done = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" *) casez (fetch_insn_valid_o) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:634" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:635" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" *) casez (\$224 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:639" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:640" */ 1'h1: insn_done = 1'h1; endcase endcase endcase (* full_case = 32'd1 *) - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:854" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:855" *) casez (exec_fsm_state) /* \nmigen.decoding = "INSN_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" */ 1'h0: /* empty */; /* \nmigen.decoding = "INSN_ACTIVE/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" *) casez (\$226 ) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" */ 1'h1: - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" *) casez (exec_pc_ready_i) - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:878" */ 1'h1: insn_done = 1'h1; endcase @@ -215078,18 +215070,18 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end pred_insn_valid_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: pred_insn_valid_i = 1'h1; endcase @@ -215097,22 +215089,22 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus always @* begin if (\initial ) begin end pred_mask_ready_i = 1'h0; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: pred_mask_ready_i = 1'h1; endcase @@ -215187,30 +215179,30 @@ module ti(rst, coresync_clk, busy_o, core_bigendian_i, pc_o, pc_i_ok, pc_i, dbus \core_core_core_cr_wr$next = core_core_core_cr_wr; \core_core_cr_wr_ok$next = core_core_cr_wr_ok; \core_core_core_is_32bit$next = core_core_core_is_32bit; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:606" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:607" *) casez (issue_fsm_state) /* \nmigen.decoding = "ISSUE_START/0" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:611" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" */ 3'h0: /* empty */; /* \nmigen.decoding = "INSN_WAIT/1" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:632" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:633" */ 3'h1: /* empty */; /* \nmigen.decoding = "PRED_START/3" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:653" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:654" */ 3'h3: /* empty */; /* \nmigen.decoding = "MASK_WAIT/4" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:658" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:659" */ 3'h4: /* empty */; /* \nmigen.decoding = "PRED_SKIP/5" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:664" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:665" */ 3'h5: /* empty */; /* \nmigen.decoding = "DECODE_SV/2" */ - /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" */ + /* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:734" */ 3'h2: { \core_core_core_is_32bit$next , \core_core_cr_wr_ok$next , \core_core_core_cr_wr$next , \core_core_core_cr_rd_ok$next , \core_core_core_cr_rd$next , \core_core_core_trapaddr$next , \core_core_core_exc_happened$next , \core_core_core_exc_segment_fault$next , \core_core_core_exc_rc_error$next , \core_core_core_exc_perm_error$next , \core_core_core_exc_badtree$next , \core_core_core_exc_invalid$next , \core_core_core_exc_instr_fault$next , \core_core_core_exc_alignment$next , \core_core_core_traptype$next , \core_core_core_input_carry$next , \core_core_core_oe_ok$next , \core_core_core_oe$next , \core_core_core_rc_ok$next , \core_core_core_rc$next , \core_core_lk$next , \core_core_core_fn_unit$next , \core_core_core_insn_type$next , \core_core_core_insn$next , \core_core_core_svstate$next , \core_core_core_cia$next , \core_core_core_msr$next , \core_core_core__SV_Ptype$next , \core_core_core__sv_saturate$next , \core_core_core__sv_pred_dz$next , \core_core_core__sv_pred_sz$next , \core_cr_out_ok$next , \core_core_cr_out$next , \core_core_cr_in2_ok$2$next , \core_core_cr_in2$1$next , \core_core_cr_in2_ok$next , \core_core_cr_in2$next , \core_core_cr_in1_ok$next , \core_core_cr_in1$next , \core_fasto3_ok$next , \core_core_fasto3$next , \core_fasto2_ok$next , \core_core_fasto2$next , \core_fasto1_ok$next , \core_core_fasto1$next , \core_core_fast3_ok$next , \core_core_fast3$next , \core_core_fast2_ok$next , \core_core_fast2$next , \core_core_fast1_ok$next , \core_core_fast1$next , \core_xer_out$next , \core_core_xer_in$next , \core_core_spr1_ok$next , \core_core_spr1$next , \core_spro_ok$next , \core_core_spro$next , \core_core_reg3_ok$next , \core_core_reg3$next , \core_core_reg2_ok$next , \core_core_reg2$next , \core_core_reg1_ok$next , \core_core_reg1$next , \core_ea_ok$next , \core_core_ea$next , \core_rego_ok$next , \core_core_rego$next , \core_asmcode$next } = { dec2_is_32bit, dec2_cr_wr_ok, dec2_cr_wr, dec2_cr_rd_ok, dec2_cr_rd, dec2_trapaddr, dec2_exc_happened, dec2_exc_segment_fault, dec2_exc_rc_error, dec2_exc_perm_error, dec2_exc_badtree, dec2_exc_invalid, dec2_exc_instr_fault, dec2_exc_alignment, dec2_traptype, dec2_input_carry, dec2_oe_ok, dec2_oe, dec2_rc_ok, dec2_rc, dec2_lk, dec2_fn_unit, dec2_insn_type, dec2_insn, dec2_svstate, dec2_cia, dec2_msr, dec2_SV_Ptype, dec2_sv_saturate, dec2_sv_pred_dz, dec2_sv_pred_sz, dec2_cr_out_ok, dec2_cr_out, \dec2_cr_in2_ok$8 , \dec2_cr_in2$7 , dec2_cr_in2_ok, dec2_cr_in2, dec2_cr_in1_ok, dec2_cr_in1, dec2_fasto3_ok, dec2_fasto3, dec2_fasto2_ok, dec2_fasto2, dec2_fasto1_ok, dec2_fasto1, dec2_fast3_ok, dec2_fast3, dec2_fast2_ok, dec2_fast2, dec2_fast1_ok, dec2_fast1, dec2_xer_out, dec2_xer_in, dec2_spr1_ok, dec2_spr1, dec2_spro_ok, dec2_spro, dec2_reg3_ok, dec2_reg3, dec2_reg2_ok, dec2_reg2, dec2_reg1_ok, dec2_reg1, dec2_ea_ok, dec2_ea, dec2_rego_ok, dec2_rego, dec2_asmcode }; endcase @@ -215657,9 +215649,9 @@ module trap0(coresync_rst, oper_i_alu_trap0__insn_type, oper_i_alu_trap0__fn_uni reg \alui_l_r_alui$next ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" *) wire alui_l_s_alui; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" *) output cu_busy_o; @@ -216726,9 +216718,9 @@ module upd_l(coresync_rst, s_upd, r_upd, q_upd, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -216788,9 +216780,9 @@ module valid_l(coresync_rst, s_valid, q_valid, r_valid, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -216873,9 +216865,9 @@ module wri_l(coresync_rst, s_wri, r_wri, q_wri, coresync_clk); wire \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" *) wire \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" *) reg q_int = 1'h0; @@ -217464,9 +217456,9 @@ module xer(coresync_rst, full_rd__ren, full_rd__data_o, src1__data_o, src1__ren, wire [1:0] \$7 ; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" *) wire [1:0] \$9 ; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_clk; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:932" *) input coresync_rst; (* src = "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" *) input [1:0] data_i; @@ -217794,7 +217786,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" *) output core_irq_o; @@ -217850,7 +217842,7 @@ module xics_icp(rst, ics_i_src, ics_i_pri, core_irq_o, icp_wb__ack, icp_wb__cyc, reg [7:0] min_pri; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" *) reg [7:0] pending_priority; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" *) reg wb_ack = 1'h0; @@ -218304,7 +218296,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc wire [31:0] be_in; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" *) reg [31:0] be_out; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input clk; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" *) reg [3:0] cur_idx0; @@ -218424,7 +218416,7 @@ module xics_ics(rst, icp_o_src, icp_o_pri, ics_wb__adr, int_level_i, ics_wb__cyc wire reg_is_debug; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" *) wire reg_is_xive; - (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:930" *) + (* src = "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:931" *) input rst; (* src = "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" *) wire wb_valid; diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v index 1bac26f..f90b6a7 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180.v @@ -1,7 +1,19 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-25 12:45:15 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-05-26 15:05:51 //-------------------------------------------------------------------------------- module ls180( + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, + input wire uart_tx, + input wire uart_rx, + input wire eint_0, + input wire eint_1, + input wire eint_2, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -14,22 +26,10 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, - input wire uart_tx, - input wire uart_rx, output wire i2c_scl, input wire i2c_sda_i, output wire i2c_sda_o, output wire i2c_sda_oe, - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, - input wire eint_0, - input wire eint_1, - input wire eint_2, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, @@ -114,7 +114,7 @@ wire libresocsim_libresoc_interface0_ack; wire libresocsim_libresoc_interface0_we; wire [2:0] libresocsim_libresoc_interface0_cti; wire [1:0] libresocsim_libresoc_interface0_bte; -wire libresocsim_libresoc_interface0_err; +reg libresocsim_libresoc_interface0_err = 1'd0; reg [28:0] libresocsim_libresoc_interface1_adr = 29'd0; reg [63:0] libresocsim_libresoc_interface1_dat_w = 64'd0; wire [63:0] libresocsim_libresoc_interface1_dat_r; @@ -125,7 +125,7 @@ wire libresocsim_libresoc_interface1_ack; wire libresocsim_libresoc_interface1_we; wire [2:0] libresocsim_libresoc_interface1_cti; wire [1:0] libresocsim_libresoc_interface1_bte; -wire libresocsim_libresoc_interface1_err; +reg libresocsim_libresoc_interface1_err = 1'd0; reg [28:0] libresocsim_libresoc_interface2_adr = 29'd0; reg [63:0] libresocsim_libresoc_interface2_dat_w = 64'd0; wire [63:0] libresocsim_libresoc_interface2_dat_r; @@ -136,7 +136,7 @@ wire libresocsim_libresoc_interface2_ack; wire libresocsim_libresoc_interface2_we; wire [2:0] libresocsim_libresoc_interface2_cti; wire [1:0] libresocsim_libresoc_interface2_bte; -wire libresocsim_libresoc_interface2_err; +reg libresocsim_libresoc_interface2_err = 1'd0; reg [28:0] libresocsim_libresoc_interface3_adr = 29'd0; reg [63:0] libresocsim_libresoc_interface3_dat_w = 64'd0; wire [63:0] libresocsim_libresoc_interface3_dat_r; @@ -147,7 +147,7 @@ wire libresocsim_libresoc_interface3_ack; wire libresocsim_libresoc_interface3_we; wire [2:0] libresocsim_libresoc_interface3_cti; wire [1:0] libresocsim_libresoc_interface3_bte; -wire libresocsim_libresoc_interface3_err; +reg libresocsim_libresoc_interface3_err = 1'd0; wire libresocsim_libresoc_jtag_tck; wire libresocsim_libresoc_jtag_tms; wire libresocsim_libresoc_jtag_tdi; @@ -159,6 +159,18 @@ wire [63:0] libresocsim_libresoc3; wire libresocsim_libresoc_pll_vco_o; wire [1:0] libresocsim_libresoc_clk_sel; wire libresocsim_libresoc_pll_test_o; +reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire libresocsim_libresoc_constraintmanager_spimaster_miso; +wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; +reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +wire libresocsim_libresoc_constraintmanager_eint_0; +wire libresocsim_libresoc_constraintmanager_eint_1; +wire libresocsim_libresoc_constraintmanager_eint_2; reg [12:0] libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -171,22 +183,10 @@ reg libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; -reg libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; wire libresocsim_libresoc_constraintmanager_i2c_scl; wire libresocsim_libresoc_constraintmanager_i2c_sda_i; wire libresocsim_libresoc_constraintmanager_i2c_sda_o; wire libresocsim_libresoc_constraintmanager_i2c_sda_oe; -reg libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire libresocsim_libresoc_constraintmanager_spimaster_miso; -wire libresocsim_libresoc_constraintmanager_eint_0; -wire libresocsim_libresoc_constraintmanager_eint_1; -wire libresocsim_libresoc_constraintmanager_eint_2; -wire [15:0] libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [29:0] libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] libresocsim_interface0_converted_interface_dat_r; @@ -6160,16 +6160,12 @@ test_issuer test_issuer( .sdr_we_n__pad__o(sdram_we_n), .sram4k_0_wb__ack(libresocsim_libresoc_interface0_ack), .sram4k_0_wb__dat_r(libresocsim_libresoc_interface0_dat_r), - .sram4k_0_wb__err(libresocsim_libresoc_interface0_err), .sram4k_1_wb__ack(libresocsim_libresoc_interface1_ack), .sram4k_1_wb__dat_r(libresocsim_libresoc_interface1_dat_r), - .sram4k_1_wb__err(libresocsim_libresoc_interface1_err), .sram4k_2_wb__ack(libresocsim_libresoc_interface2_ack), .sram4k_2_wb__dat_r(libresocsim_libresoc_interface2_dat_r), - .sram4k_2_wb__err(libresocsim_libresoc_interface2_err), .sram4k_3_wb__ack(libresocsim_libresoc_interface3_ack), - .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r), - .sram4k_3_wb__err(libresocsim_libresoc_interface3_err) + .sram4k_3_wb__dat_r(libresocsim_libresoc_interface3_dat_r) ); endmodule -- 2.30.2