From 55f4ef09a7fadc95c4d11f6be4937221460eea77 Mon Sep 17 00:00:00 2001 From: "pham.michael.98@a029fe8ac2da19fcd7269c492cf0410b2e5fd4cc" Date: Sat, 14 Sep 2019 20:52:01 +0100 Subject: [PATCH] Initial creation of resources/specs page --- resources.mdwn | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 resources.mdwn diff --git a/resources.mdwn b/resources.mdwn new file mode 100644 index 000000000..6a4d133a3 --- /dev/null +++ b/resources.mdwn @@ -0,0 +1,23 @@ +# This page aims to collect all the resources and specifications we need in one place for quick access. + +We will try our best to keep links here up-to-date. Feel free to add more links here. + +# RISC-V Instruction Set Architecture + +The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name of the project implies, we will be following the RISC-V ISA due to it being open-source and also because of the huge software and hardware ecosystem building around it. There are other open-source ISAs but none of them have the same momentum and energy behind it as RISC-V. + +To fully take advantage of the RISC-V ecosystem, it is important to be compliant with the RISC-V standards. Doing so will allow us to to reuse most software as-is and avoid major forks. + +* Official compiled PDFs of RISC-V ISA Manual: +* Working draft of the proposed RISC-V Bitmanipulation extension: +* RISC-V "V" Vector Extension: + +Note: As far as I know, we aren't using the RISC-V V Extension directly at the moment. But, I am putting it here for informative comparison purposes to our own vector extension called SV. + +# IEEE Standard for Floating-Point Arithmetic (IEEE 754) + +Almost all modern computers follow the IEEE Floating-Point Standard. Of course, we will follow it as well for interoperability. + +* + +Note: Even though this is such an important standard used by everyone, it is unfortunately not freely available and requires a payment to access. However, each of the Libre RISC-V members already have access to the document. -- 2.30.2