From 5a9ad05a05a8c610beafff175a5bd38234084861 Mon Sep 17 00:00:00 2001
From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0"
 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Sun, 1 Nov 2020 22:26:23 +0000
Subject: [PATCH]

---
 HDL_workflow/fpga.mdwn | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/HDL_workflow/fpga.mdwn b/HDL_workflow/fpga.mdwn
index d62fe95e5..5ff231436 100644
--- a/HDL_workflow/fpga.mdwn
+++ b/HDL_workflow/fpga.mdwn
@@ -54,7 +54,11 @@ lkcl:
 
 ## Connecting the dots:
 
-litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
+Accurate render of board for reference <https://github.com/emard/ulx3s/blob/master/pic/ulx3st.jpg>
+
+STLINKV2 Pins and JTAG signals schematic/user guide <https://www.st.com/resource/en/user_manual/dm00026748-stlinkv2-incircuit-debuggerprogrammer-for-stm8-and-stm32-stmicroelectronics.pdf>
+
+Litex platform file <https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/ulx3s.py>
 
     ("gpio", 0,
         Subsignal"p", Pins("B11")),
-- 
2.30.2