From 5ab1b4032a7c979ac520d9285640816ac7c760e7 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 18 Jun 2018 05:00:28 +0100
Subject: [PATCH] add slides

---
 pinmux/pinmux_chennai_2018.tex               | 18 ++++++++++++++++++
 simple_v_extension/simple_v_chennai_2018.tex |  8 ++++----
 2 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/pinmux/pinmux_chennai_2018.tex b/pinmux/pinmux_chennai_2018.tex
index 82d3170aa..391d241f2 100644
--- a/pinmux/pinmux_chennai_2018.tex
+++ b/pinmux/pinmux_chennai_2018.tex
@@ -176,6 +176,24 @@
  \end{center}
 }
 
+\frame{\frametitle{Pin Configuration, input and output}
+
+ \begin{itemize}
+   \item Standard Mux design {\bf cannot deal with many-to-one inputs}\\
+	     (SiFive IOF source code from Freedom U310 cannot, either)
+	     \vspace{4pt}
+   \item I/O pad configuration conflated with Muxer conflated with GPIO
+         conflated with EINT
+         	     \vspace{4pt}
+   \item Need to separate all of these out
+            	     \vspace{4pt}
+   \item EINTs to be separate FNs (managed by RISC-V PLIC)
+            	     \vspace{4pt}
+   \item GPIO In/Out/Direction treated just like any other FN
+            	     \vspace{4pt}
+   \item Pad configuration separated and given one-to-one Registers
+ \end{itemize}
+}
 
 \frame{\frametitle{Register-to-pad "control" settings}
  \begin{center}
diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 0fc04eb5c..14e593c43 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -301,15 +301,15 @@ for (int i = 0; i < VL; ++i)
 \frametitle{Register key-value CSR table decoding pseudocode}
 
 \begin{semiverbatim}
-struct vectorised fp\_vec[32], int\_vec[32]; // 64 in future
+struct vectorised fp\_vec[32], int\_vec[32];
 for (i = 0; i < 16; i++) // 16 CSRs?
    tb = int\_vec if CSRvec[i].type == 0 else fp\_vec
    idx = CSRvec[i].regkey // INT/FP src/dst reg in opcode
    tb[idx].elwidth  = CSRvec[i].elwidth
    tb[idx].regidx   = CSRvec[i].regidx  // indirection
+   tb[idx].regidx  += CSRvec[i].bank << 5 // 0 (1=rsvd)
    tb[idx].isvector = CSRvec[i].isvector
    tb[idx].packed   = CSRvec[i].packed  // SIMD or not
-   tb[idx].bank     = CSRvec[i].bank    // 0 (1=rsvd)
    tb[idx].enabled  = true
 \end{semiverbatim}
 
@@ -344,14 +344,14 @@ for (i = 0; i < 16; i++) // 16 CSRs?
 \frametitle{Predication key-value CSR table decoding pseudocode}
 
 \begin{semiverbatim}
-struct pred fp\_pred[32], int\_pred[32]; // 64 in future
+struct pred fp\_pred[32], int\_pred[32];
 for (i = 0; i < 16; i++) // 16 CSRs?
    tb = int\_pred if CSRpred[i].type == 0 else fp\_pred
    idx = CSRpred[i].regkey
    tb[idx].zero     = CSRpred[i].zero    // zeroing
    tb[idx].inv      = CSRpred[i].inv     // inverted
    tb[idx].predidx  = CSRpred[i].predidx // actual reg
-   tb[idx].bank     = CSRpred[i].bank    // 0 for now
+   tb[idx].predidx += CSRvec[i].bank << 5 // 0 (1=rsvd)
    tb[idx].enabled  = true
 \end{semiverbatim}
 
-- 
2.30.2