From 608ce98a004c001a89fa597eb15a69b361943857 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 17 Jun 2018 06:32:40 +0100
Subject: [PATCH] add DDR link

---
 shakti/m_class.mdwn | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 6dc5420d4..9f96863e4 100644
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -217,7 +217,7 @@ TBD
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
 Some interfaces at:
@@ -235,6 +235,7 @@ Some interfaces at:
 List of Interfaces:
 
 * [[CSI]]
+* [[DDR]]
 * [[JTAG]]
 * [[I2C]]
 * [[I2S]]
-- 
2.30.2