From 6b67680fd5b9e2cf2be04e0018a0fc74cfd89c4a Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 12:01:53 +0100 Subject: [PATCH] --- ...lysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index bd1a74781..03a1d9b03 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -2,7 +2,8 @@ ## Register file -The harmonised RVP register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16] +The default Harmonised RVP GPR register file is divided into a lower bank of Vector[INT8] and an upper bank of Vector[INT16] +In contrast, the Andes Packed SIMD ISA permits any GPR to be used for either INT8 or INT16 vector operations | Register | Andes ISA | Harmonised RVP ISA | | ------------------ | ------------------------- | ------------------- | -- 2.30.2