From 6c2d1f168ea7042985287c330b3ff533d8aa7603 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 14 Jul 2020 11:41:41 +0100 Subject: [PATCH] attempting running cxxsim on ALU pipeline test --- src/soc/fu/alu/test/test_pipe_caller.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index 9201c008..88b61b70 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -1,5 +1,11 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle +from nmigen.back.pysim import Delay, Settle +cxxsim = False +if cxxsim: + from nmigen.sim.cxxsim import Simulator +else: + from nmigen.back.pysim import Simulator + from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest @@ -242,9 +248,12 @@ class TestRunner(FHDLTestCase): yield from self.check_alu_outputs(alu, pdecode2, sim, code) sim.add_sync_process(process) - with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw", - traces=[]): - sim.run() + if cxxsim: + sim.run() + else: + with sim.write_vcd("alu_simulator.vcd", "simulator.gtkw", + traces=[]): + sim.run() def check_alu_outputs(self, alu, dec2, sim, code): -- 2.30.2