From 6d826d32103df9c502bc4a561d47677b1333d76d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 12 Jul 2018 03:07:56 +0100 Subject: [PATCH] add slids --- shakti/m_class/libre_riscv_chennai_2018.tex | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/shakti/m_class/libre_riscv_chennai_2018.tex b/shakti/m_class/libre_riscv_chennai_2018.tex index 536afd6e3..e218acd5c 100644 --- a/shakti/m_class/libre_riscv_chennai_2018.tex +++ b/shakti/m_class/libre_riscv_chennai_2018.tex @@ -273,7 +273,7 @@ \end{itemize} {\it Jacob Bachmeyer's Cache-control proposal turns L1 Cache into scratchpad RAM. RVV is just too heavy (sorry!), Simple-V much - more light-weight and flexible. + more light-weight and flexible ($O(1)$ ISA proliferation) } } @@ -289,7 +289,20 @@ \frame{\frametitle{Summary} \begin{itemize} - \item TODO + \item Making a commercially-desirable SoC is neither academically + nor standard-investor sexy! No AI. Boring. zzzz + \item Luckily there is an anonymous sponsor who needs an SoC that + doesn't exist (who knows the commercial benefits of Libre) + \item Shakti Group know the benefits (cost, sovereignty) of a Libre + Mobile-Class SoC as well (No spying on India citizens!) + \item A Libre GPU, even a modest performer (100T/s etc.) + is the biggest technical risk / unknown (besides DDR3/4).\\ + (fall-back is GC800. Do please help with a Libre GPU!) + \item DDR3/4 and eMMC are the main high-risk interfaces\\ + (there are fall-back strategies in place) + \item Ultimately the strategy is all about cost reduction + vs risk mitigation, + with Libre/Ethical prioritised over "convenience" \end{itemize} } -- 2.30.2