From 6fe174d9e78e3181e76d369d9988fd4a3577120c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Jul 2020 14:45:09 +0100 Subject: [PATCH] increase range of test values for extswsli --- src/soc/fu/shift_rot/test/test_pipe_caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index f19ba4d3..ec35aaae 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -153,7 +153,7 @@ class ShiftRotTestCase(FHDLTestCase): sh = random.randint(0, 63) lst = [f"extswsli 3, 1, {sh}"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<15)-1) + initial_regs[1] = random.randint(0, (1<<64)-1) self.run_tst_program(Program(lst, bigendian), initial_regs) def test_rlc(self): -- 2.30.2