From 72b76bb9bf572d757acb3a24c0d6f64e1d2f0ae8 Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 11:50:44 +0100 Subject: [PATCH] --- ...alysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn index 69dd23ca8..a28f8cfe9 100644 --- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn +++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn @@ -22,7 +22,7 @@ The harmonised RVP register file is divided into a lower bank of Vector[INT8] an | v13 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | | v14 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | | v15 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[4xUINT8] | -| ------------------ | ------------------------- | ------------------- | +| | | | | v16 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | | v17 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | | v18 | 32bit GPR or Vector[4xINT8 or 2xINT16] | 32bit GPR or Vector[2xSINT16] | -- 2.30.2