From 764df562cc2a90debc17a9678e8b4a49e7916571 Mon Sep 17 00:00:00 2001 From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0" Date: Sun, 22 Nov 2020 20:20:58 +0000 Subject: [PATCH] --- HDL_workflow/ECP5_FPGA.mdwn | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn index 1cdd0e7e2..11134812a 100644 --- a/HDL_workflow/ECP5_FPGA.mdwn +++ b/HDL_workflow/ECP5_FPGA.mdwn @@ -191,9 +191,8 @@ Table of connections: | X3 pin # | FPGA IO PAD | STLinkv2 |Wire Colour| |-------------|-------------|----------------|-----------| -|1 GND | GND | 4 (GND) | Black | -|2 NC | NC | NC | NC | |39 +3.3V | 3.3V supply | 2 (MCU VDD) | Red | +|1 GND | GND | 4 (GND) | Black | |4 IO29 | B19 | 5 (TDI) | Green | |5 IO30 | B12 | 7 (TMS) | Blue | |6 IO31 | B9 | 9 (TCK) | White | -- 2.30.2