From 788770e7dca7b92bdf4133329af4f09633faf298 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 24 Jul 2019 11:24:42 +0100
Subject: [PATCH] fix shifting of rsqrt mantissa input

---
 src/ieee754/div_rem_sqrt_rsqrt/core.py | 2 +-
 src/ieee754/fpcommon/test/fpmux.py     | 3 ++-
 src/ieee754/fpdiv/div0.py              | 4 ++--
 3 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 2e524038..1c1e4c29 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -249,7 +249,7 @@ class DivPipeCoreSetupStage(Elaboratable):
                 self.i.divisor_radicand << (self.core_config.fract_width * 2))
         with m.Else():  # DivPipeCoreOperation.RSqrtRem
             m.d.comb += self.o.compare_lhs.eq(
-                1 << (self.core_config.fract_width * 2))
+                1 << (self.core_config.fract_width * 2)) # XXX reduced from 3
 
         m.d.comb += self.o.compare_rhs.eq(0)
         m.d.comb += self.o.operation.eq(self.i.operation)
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index ef0a2f33..f07ca658 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -171,6 +171,7 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op1 = 0x4800
                 #op1 = 0x48f0
                 #op1 = 0x429
+                #op1 = 0x2631
 
                 vals.append((op1,))
             else:
@@ -183,7 +184,7 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 #op2 = 0xb371
                 #op1 = 0x4400
                 #op1 = 0x656c
-                op1 = 0x738c
+                #op1 = 0x738c
 
                 vals.append((op1, op2,))
     return vals
diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 0c9ed334..c93ba723 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -121,8 +121,8 @@ class FPDivStage0Mod(Elaboratable):
                     m.d.comb += am0.eq(Cat(self.i.a.m, 0)<<(extra-3))
                     m.d.comb += self.o.z.e.eq(-((self.i.a.e+1) >> 1)+4)
                 with m.Else():
-                    m.d.comb += am0.eq(Cat(0, self.i.a.m)<<(extra-3))
-                    m.d.comb += self.o.z.e.eq((self.i.a.e >> 1)+2)
+                    m.d.comb += am0.eq(Cat(self.i.a.m)<<(extra-2))
+                    m.d.comb += self.o.z.e.eq(-(self.i.a.e >> 1)+4)
 
                 m.d.comb += [self.o.z.s.eq(self.i.a.s),
                              self.o.divisor_radicand.eq(am0),
-- 
2.30.2