From 7a04c23586a308b253204d4203ad5cecdba3bc34 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 18 Jun 2019 10:03:52 +0100 Subject: [PATCH] clarify comment --- src/experiment/compldst.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/experiment/compldst.py b/src/experiment/compldst.py index e2fccf87..5754da5b 100644 --- a/src/experiment/compldst.py +++ b/src/experiment/compldst.py @@ -214,7 +214,7 @@ class LDSTCompUnit(Elaboratable): with m.If(~self.alu.p_ready_o): # no ACK yet m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid - # put the register directly onto the output + # put the register directly onto the output bus with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)): comb += self.data_o.eq(data_r) -- 2.30.2