From 7ebe0bda3440e9ccaddd9f769fc966b8b4343897 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Thu, 8 Oct 2020 17:45:32 -0700 Subject: [PATCH] move mul pipe ilang test to separate file --- src/soc/fu/mul/test/test_pipe_caller.py | 13 +++---------- src/soc/fu/mul/test/test_pipe_ilang.py | 20 ++++++++++++++++++++ 2 files changed, 23 insertions(+), 10 deletions(-) create mode 100644 src/soc/fu/mul/test/test_pipe_ilang.py diff --git a/src/soc/fu/mul/test/test_pipe_caller.py b/src/soc/fu/mul/test/test_pipe_caller.py index 8742ef7f..756d10f4 100644 --- a/src/soc/fu/mul/test/test_pipe_caller.py +++ b/src/soc/fu/mul/test/test_pipe_caller.py @@ -171,16 +171,9 @@ class MulTestCase(TestAccumulatorBase): initial_regs[2] = 0x0000000000000002 self.add_case(Program(lst, bigendian), initial_regs) -# TODO add test case for these 3 operand cases (madd -# needs to be implemented) -# "maddhd","maddhdu","maddld" - - def case_ilang(self): - pspec = MulPipeSpec(id_wid=2) - alu = MulBasePipe(pspec) - vl = rtlil.convert(alu, ports=alu.ports()) - with open("mul_pipeline.il", "w") as f: - f.write(vl) + # TODO add test case for these 3 operand cases (madd + # needs to be implemented) + # "maddhd","maddhdu","maddld" class TestRunner(unittest.TestCase): diff --git a/src/soc/fu/mul/test/test_pipe_ilang.py b/src/soc/fu/mul/test/test_pipe_ilang.py new file mode 100644 index 00000000..22af35ba --- /dev/null +++ b/src/soc/fu/mul/test/test_pipe_ilang.py @@ -0,0 +1,20 @@ +import unittest +from nmigen.cli import rtlil +from soc.fu.mul.pipe_data import MulPipeSpec +from soc.fu.mul.pipeline import MulBasePipe + + +class TestPipeIlang(unittest.TestCase): + def write_ilang(self): + pspec = MulPipeSpec(id_wid=2) + alu = MulBasePipe(pspec) + vl = rtlil.convert(alu, ports=alu.ports()) + with open("mul_pipeline.il", "w") as f: + f.write(vl) + + def test_ilang(self): + self.write_ilang() + + +if __name__ == "__main__": + unittest.main() -- 2.30.2