From 809f6265ce59b8ec94a2efd6a23b9a4574d444b2 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Jul 2018 05:47:28 +0100 Subject: [PATCH] uart clock and reset --- src/bsv/peripheral_gen/quart.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/bsv/peripheral_gen/quart.py b/src/bsv/peripheral_gen/quart.py index 14e0808..83fd810 100644 --- a/src/bsv/peripheral_gen/quart.py +++ b/src/bsv/peripheral_gen/quart.py @@ -14,7 +14,7 @@ class quart(PBase): "method Bit#(1) %s;" % self.irq_name() def get_clock_reset(self, name, count): - return "uart_clock,uart_reset" # XXX TODO: change to uart_clock/reset + return "uart_clock,uart_reset" def num_axi_regs32(self): return 8 @@ -76,7 +76,7 @@ class quart(PBase): uart_plic_template = """\ // PLIC {0} synchronisation with irq {1} SyncBitIfc#(Bit#(1)) {0}_interrupt <- - mkSyncBitToCC(sp_clock, uart_reset); + mkSyncBitToCC(uart_clock, uart_reset); rule plic_synchronize_{0}_interrupt_{1}; {0}_interrupt.send({0}.irq); endrule -- 2.30.2