From 858f9396e344199eb60526db0d4f129089306334 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 29 Jun 2022 10:12:29 +0100 Subject: [PATCH] reduce wordage --- svp64-primer/summary.tex | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex index 029d1618f..318125d8b 100644 --- a/svp64-primer/summary.tex +++ b/svp64-primer/summary.tex @@ -4,7 +4,7 @@ ONLY uses scalar instructions}. \begin{itemize} \itemsep 0em -\item The Power \acs{ISA} v3.1 Specification is not altered in any way. +\item The Power \acs{ISA} v3.1 Spec is not altered. v3.1 Code-compatibility is guaranteed. \item Does not require sacrificing 32-bit Major Opcodes. \item Does not require adding duplicates of instructions @@ -20,7 +20,7 @@ ONLY uses scalar instructions}. \item At the highest Compliancy Level only requires five instructions (SVE2 requires appx 9,000. \acs{AVX-512} around 10,000. \acs{RVV} around 300). -\item Predication, an often-requested feature, is added cleanly +\item Predication, often-requested, is added cleanly (without modifying the v3.1 Power ISA) \item In-registers arbitrary-sized Matrix Multiply is achieved in three instructions (without adding any v3.1 Power ISA instructions) @@ -40,9 +40,7 @@ size, which as outlined in \cite{SIMD_HARM} has an indirect reduction in power consumption due to less I-Cache/TLB pressure and also Issue remaining idle for long periods. Simple-V has been specifically and carefully crafted to respect -the Power ISA's Supercomputing pedigree, and very specifically crafted -to fit on top of both simple single-issue and complex multi-issue -Superscalar Micro-Architectures. +the Power ISA's Supercomputing pedigree. \begin{figure}[hb] \centering -- 2.30.2