From 86aad8c209609e69d6d100255afd06546c71ac1e Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 13 Apr 2023 12:56:20 +0100 Subject: [PATCH] spotted that the Shifted-only group of LD/ST-Post-increment needs to be in EXT0xx but that Shifted-Post-Increment can be in EXT2xx i think. ls011 --- openpower/sv/rfc/ls004.mdwn | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls004.mdwn b/openpower/sv/rfc/ls004.mdwn index cf687d3a8..6acb74ef2 100644 --- a/openpower/sv/rfc/ls004.mdwn +++ b/openpower/sv/rfc/ls004.mdwn @@ -105,14 +105,20 @@ costly. The totals are * 3 Store Indexed Shifted Byte-reverse * 6 Floating-Point Load Indexed Shifted (with Update) * 6 Floating-Point Store Indexed Shifted (with Update) +* 6 Load Indexed Shifted Update Post-Increment +* 4 Store Indexed Shifted Update Post-Increment +* 2 Floating-Point Load Indexed Shifted Update Post-Increment +* 2 Floating-Point Store Indexed Shifted Update Post-Increment -Total count: 38 new 9-bit XO instructions, for an approximate total +Total count: 51 new 9-bit XO instructions, for an approximate total XO cost of 3 bits within a single Primary Opcode. With the savings that these instructions represent in hot-loops, as evidenced by their inclusion in top-end ISAs such as x86 and ARM, the cost may be considered -justifiable. However there is no point in placing these in EXT2xx, they -need to be in EXT0xx, because if added as 64-bit Encoding the benefit -reduction in binary size is not achieved. +justifiable. However there is no point in placing the 38 +Shifted-only group in EXT2xx, they need to be in EXT0xx, because if added +as 64-bit Encoding the benefit reduction in binary size is not achieved. +Post-Increment-Shifted on the other hand could reasonably be proposed +in EXT2xx. | 0-5 | 6-10 | 11-15 | 16-20 | 21-22 | 23-31 | Instruction | |-------|------|-------|-------|-------|-------|----------------------| @@ -153,6 +159,20 @@ reduction in binary size is not achieved. | PO | FRS | RA | RB | sm | XO | stfdxs FRS,RA,RB,sm | | PO | FRS | RA | RB | sm | XO | stfduxs FRS,RA,RB,sm | | PO | FRS | RA | RB | sm | XO | stfiwxs FRS,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lbzuspx RT,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lhzuspx RT,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lhauspx RT,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lwzuspx RT,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lwauspx RT,RA,RB,sm | +| PO | RS | RA | RB | sm | XO | stbuspx RS,RA,RB,sm | +| PO | RS | RA | RB | sm | XO | sthuspx RS,RA,RB,sm | +| PO | RS | RA | RB | sm | XO | stwuspx RS,RA,RB,sm | +| PO | RS | RA | RB | sm | XO | stduspx RS,RA,RB,sm | +| PO | RT | RA | RB | sm | XO | lduspx RT,RA,RB,sm | +| PO | FRT | RA | RB | sm | XO | lfdupxs FRT,RA,RB,sm | +| PO | FRT | RA | RB | sm | XO | lfsupxs FRT,RA,RB,sm | +| PO | FRS | RA | RB | sm | XO | stfdupxs FRS,RA,RB,sm | +| PO | FRS | RA | RB | sm | XO | stfsupxs FRS,RA,RB,sm | ---------------- -- 2.30.2