From 8b208495536795b629c72a3d06ef3cd77aab73a0 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Thu, 7 Apr 2022 16:36:51 -0500 Subject: [PATCH] Update coldboot DDR3 init firmware to work with latest gram changes --- coldboot/Makefile | 4 +- coldboot/coldboot.c | 121 +++++++++++++++++++++++++++++++++++--------- libgram/src/dfii.c | 11 +--- 3 files changed, 100 insertions(+), 36 deletions(-) diff --git a/coldboot/Makefile b/coldboot/Makefile index 4a90fe6..afab3c7 100644 --- a/coldboot/Makefile +++ b/coldboot/Makefile @@ -15,8 +15,8 @@ SHORT_TIMER_MULT = 100 # SPI boot address 0x1000_0000, main SRAM boot would be 0x0000_0000 # but remember to recompile external_core_top.v with a matching # --pc_reset=0xNNNNNNNN -BOOT_INIT_BASE ?= 0x10000000 -# BOOT_INIT_BASE ?= 0x0 +# BOOT_INIT_BASE ?= 0x10000000 +BOOT_INIT_BASE ?= 0x0 LIBGRAMDIR = ../libgram LIBGRAMINC = ../libgram/include diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c index 90a5698..31e081f 100644 --- a/coldboot/coldboot.c +++ b/coldboot/coldboot.c @@ -58,36 +58,62 @@ void isr(void) { } +// XXX +// Defining gram_[read|write] allows a trace of all register +// accesses to be dumped to console for debugging purposes. +// To use, define GRAM_RW_FUNC in gram.h +uint32_t gram_read(const struct gramCtx *ctx, void *addr) { + uint32_t dword; + + puts("gram_read: "); + uart_writeuint32(addr); + dword = readl(addr); + puts(": "); + uart_writeuint32(dword); + puts("\n"); + + return dword; +} + +int gram_write(const struct gramCtx *ctx, void *addr, uint32_t value) { + puts("gram_write: "); + uart_writeuint32(addr); + puts(": "); + uart_writeuint32(value); + writel(value, addr); + puts("\n"); + + return 0; +} + int main(void) { const int kNumIterations = 14; int res, failcnt = 0, i=0; uint32_t tmp; volatile uint32_t *ram = (uint32_t*)DRAM_BASE; + console_init(); //puts("Firmware launched...\n"); puts("fw.."); +#if 0 #if 1 // print out configuration parameters for QSPI volatile uint32_t *qspi_cfg = (uint32_t*)0xc0003000; - for (int k=0; k < 10; k++) { + for (int k=0; k < 2; k++) { tmp = readl((unsigned long)&(qspi_cfg[k])); - puts("cfg"); - uart_writeuint32(k); - puts(" "); - uart_writeuint32(tmp); - puts("\n"); + //puts("cfg"); + //uart_writeuint32(k); + //puts(" "); + //uart_writeuint32(tmp); + //puts("\n"); } - +#endif volatile uint32_t *qspi = (uint32_t*)0x10000000; - volatile uint8_t *qspi_bytes = (uint8_t*)0x10000000; - // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0])); - // tmp = readl((unsigned long)&(qspi[0])); -for (i=0;i<1000;i++) { - writel(0xDEAF0123+i, (unsigned long)&(qspi[i])); -} + volatile uint8_t *qspi_bytes = (uint8_t*)0x10000000; + // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0])); + // tmp = readl((unsigned long)&(qspi[0])); for (i=0;i<1000;i++) { - if (i%8 == 0) puts("\r\n"); tmp = readl((unsigned long)&(qspi[i])); uart_writeuint32(tmp); puts(" "); @@ -95,12 +121,11 @@ for (i=0;i<1000;i++) { putchar(10); putchar(10); for (i=0;i<1000;i++) { - if (i%8 == 0) puts("\r\n"); tmp = readb((unsigned long)&(qspi_bytes[i])); uart_writeuint32(tmp); puts(" "); } -#if 0 +#if 1 while (1) { // quick read tmp = readl((unsigned long)&(qspi[0x1000/4])); @@ -154,19 +179,44 @@ for (i=0;i<1000;i++) { puts("DRAM init... "); struct gramCtx ctx; +#if 1 + struct gramProfile profile = { + .mode_registers = { + 0xb20, 0x806, 0x200, 0x0 + }, + .rdly_p0 = 2, + .rdly_p1 = 2, + }; +#endif +#if 0 struct gramProfile profile = { .mode_registers = { - 0x320, 0x6, 0x200, 0x0 + 0x0320, 0x0006, 0x0200, 0x0000 }, - .rdly_p0 = 5, - .rdly_p1 = 5, + .rdly_p0 = 1, + .rdly_p1 = 1, }; +#endif struct gramProfile profile2; - gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000, - (void*)DRAM_CTRL_BASE, //0x00009000, - (void*)DRAM_INIT_BASE); //0x00008000); + gram_init(&ctx, &profile, (void*)DRAM_BASE, + (void*)DRAM_CTRL_BASE, + (void*)DRAM_INIT_BASE); puts("done\n"); + puts("MR profile: "); + uart_writeuint32(profile.mode_registers[0]); + puts(" "); + uart_writeuint32(profile.mode_registers[1]); + puts(" "); + uart_writeuint32(profile.mode_registers[2]); + puts(" "); + uart_writeuint32(profile.mode_registers[3]); + puts("\n"); + + // FIXME + // Early read test for WB access sim + //uart_writeuint32(*ram); + #if 1 puts("Rdly\np0: "); for (size_t i = 0; i < 8; i++) { @@ -211,20 +261,23 @@ for (i=0;i<1000;i++) { } puts("done\n"); -#endif - puts("Auto calibration profile:"); puts("p0 rdly:"); uart_writeuint32(profile2.rdly_p0); puts(" p1 rdly:"); uart_writeuint32(profile2.rdly_p1); puts("\n"); +#endif + + puts("Reloading built-in calibration profile..."); + gram_load_calibration(&ctx, &profile); puts("DRAM test... \n"); for (size_t i = 0; i < kNumIterations; i++) { writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i])); } +#if 0 for (int dly = 0; dly < 8; dly++) { failcnt = 0; profile2.rdly_p0 = dly; @@ -239,7 +292,7 @@ for (i=0;i<1000;i++) { puts("fail : *(0x"); uart_writeuint32((unsigned long)(&ram[i])); puts(") = "); - uart_writeuint32(ram[i]); + uart_writeuint32(readl((unsigned long)&(ram[i]))); puts("\n"); failcnt++; @@ -250,6 +303,24 @@ for (i=0;i<1000;i++) { } } } +#else + failcnt = 0; + for (size_t i = 0; i < kNumIterations; i++) { + if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) { + puts("fail : *(0x"); + uart_writeuint32((unsigned long)(&ram[i])); + puts(") = "); + uart_writeuint32(readl((unsigned long)&(ram[i]))); + puts("\n"); + failcnt++; + + if (failcnt > 10) { + puts("Test canceled (more than 10 errors)\n"); + break; + } + } + } +#endif puts("done\n"); return 0; diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c index 3d87345..777c17a 100644 --- a/libgram/src/dfii.c +++ b/libgram/src/dfii.c @@ -14,18 +14,11 @@ static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) { #endif } -void dfii_reset(const struct gramCtx *ctx) { - dfii_set_p0_address(ctx, 0); - dfii_set_p0_baddress(ctx, 0); - dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET); -} - void dfii_setsw(const struct gramCtx *ctx, bool software_control) { if (software_control) { - dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT| - DFII_CONTROL_RESET); + dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET|DFII_COMMAND_CS); } else { - dfii_setcontrol(ctx, DFII_CONTROL_SEL); + dfii_setcontrol(ctx, DFII_CONTROL_SEL|DFII_CONTROL_RESET); } } -- 2.30.2