From 8d9f6cc6b313eb82bf01892d95ae84f43c42693d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 30 Apr 2018 09:07:13 +0100 Subject: [PATCH] add state information section --- isa_conflict_resolution/mvendor_march_warl.mdwn | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/isa_conflict_resolution/mvendor_march_warl.mdwn b/isa_conflict_resolution/mvendor_march_warl.mdwn index 0d75b2c0b..2cb1ea348 100644 --- a/isa_conflict_resolution/mvendor_march_warl.mdwn +++ b/isa_conflict_resolution/mvendor_march_warl.mdwn @@ -66,6 +66,10 @@ needs discussion, as it would be unfortunate and undesirable for a hybrid processor capable of executing more than one hardware-level ISA support to not be permitted to receive RISC-V Certification Compliance. +How such foreign architectures would switch back to RISC-V when the foreign +architecture does not support the concept of mvendorid-marchid is out of +scope and left to implementors. + ## Implementation The redirection of meaning of certain binary encodings to multiple -- 2.30.2