From 917d4b6adc513e22dc616808e62e3475ab889ea1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 11:29:40 +0100 Subject: [PATCH] clarify --- simple_v_extension.mdwn | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index d3aca4d47..bd4c44b2e 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -357,7 +357,7 @@ level all-hardware parallelism. Options are covered in the Appendix. # CSRs There are a number of CSRs needed, which are used at the instruction -decode phase to re-interpret standard RV opcodes (a practice that has +decode phase to re-interpret RV opcodes (a practice that has precedent in the setting of MISA to enable / disable extensions). * Integer Register N is Vector of length M: r(N) -> r(N..N+M-1) @@ -377,6 +377,8 @@ Notes: "bitwidth" may fit into an XLEN-sized register file. * Predication is a key-value store due to the implicit referencing, as opposed to having the predicate register explicitly in the instruction. +* Whilst the predication CSR is a key-value store it *generates* easier-to-use + state information. ## Predication CSR -- 2.30.2