From 95a74ba3566333ac498bb1110781e563f86b4c06 Mon Sep 17 00:00:00 2001 From: Andrey Miroshnikov Date: Tue, 1 Nov 2022 18:49:54 +0000 Subject: [PATCH] ls004: Adjusted word desc based on Lukes c#10, bug #968 --- openpower/sv/rfc/ls004.mdwn | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/openpower/sv/rfc/ls004.mdwn b/openpower/sv/rfc/ls004.mdwn index a8afce0c3..80825cd39 100644 --- a/openpower/sv/rfc/ls004.mdwn +++ b/openpower/sv/rfc/ls004.mdwn @@ -68,8 +68,10 @@ Replaces a pair of explicit instructions in hot-loops. **Notes and Observations**: 1. `shadd` and `shadduw` operate on unsigned integers. -2. `shadduw` masks the upper 32-bits of the operand to-be-shifted. -3. These are both 2-in 1-out instructions. +2. `shadduw` is intended for performing address offsets, + as the second operand is constrained to lower 32-bits + and sign-extended. +3. Both are 2-in 1-out instructions. **Changes** @@ -122,17 +124,21 @@ shadd r4, r1, r2, 3 Pseudocode: shift <- sm + 1 # Shift is between 1-4 - n <- (RB)[XLEN/2:XLEN-1] # Limit RB to upper word (32-bits) + n <- (RB)[32:63] # Only use lower 32-bits of RB sum[0:63] <- (n << shift) + (RA) # Shift n, add RA RT <- sum # Result stored in RT -When `sm` is zero, the upper word contents of register RB are multiplied by 2, +When `sm` is zero, the lower word contents of register RB are multiplied by 2, added to the contents of register RA, and the result stored in RT. `sm` is a 2-bit bitfield, and allows multiplication of RB by 2, 4, 8, 16. Operands RA and RB, and the result RT are all 64-bit, unsigned integers. +*Programmer's Note: +The advantage of this instruction is doing address offsets. RA is the base 64-bit +address. RB is the offset into data structure limited to 32-bit. + Examples: ``` -- 2.30.2