From 970fbd01a62def52675c9e398386b8ce0536e0d9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 12 Mar 2021 14:12:41 +0000 Subject: [PATCH] remove old code --- .gitmodules | 3 + src/soc/litex/core.py | 143 --------------- src/soc/litex/florent | 1 + src/soc/litex/florent/microwatt/boot-helper.S | 4 - src/soc/litex/florent/microwatt/crt0.S | 93 ---------- .../litex/{florent => florent_old}/Makefile | 0 .../litex/{florent => florent_old}/README.txt | 0 .../SPBlock_512W64B8W.v | 0 .../{florent => florent_old}/idcode_test.svf | 0 .../{florent => florent_old}/idcode_test2.svf | 0 .../libresoc/__init__.py | 0 .../{ => florent_old/libresoc}/boot-helper.S | 0 .../{florent => florent_old}/libresoc/core.py | 0 .../litex/{ => florent_old/libresoc}/crt0.S | 0 .../{florent => florent_old}/libresoc/irq.h | 0 .../libresoc/ls180.py | 0 .../libresoc/system.h | 0 .../{florent => florent_old}/ls180pins.txt | 0 .../{florent => florent_old}/ls180soc.py | 0 .../microwatt/__init__.py | 0 .../microwatt}/boot-helper.S | 0 .../microwatt/core.py | 0 .../libresoc => florent_old/microwatt}/crt0.S | 0 .../{florent => florent_old}/microwatt/irq.h | 0 .../microwatt/microwatt.v | 0 .../microwatt/system.h | 0 .../{florent => florent_old}/openocd.cfg | 0 src/soc/litex/{florent => florent_old}/sim.py | 0 .../{florent => florent_old}/versa_ecp5.py | 0 src/soc/litex/irq.h | 33 ---- src/soc/litex/sim.py | 165 ------------------ src/soc/litex/system.h | 18 -- 32 files changed, 4 insertions(+), 456 deletions(-) delete mode 100644 src/soc/litex/core.py create mode 160000 src/soc/litex/florent delete mode 100644 src/soc/litex/florent/microwatt/boot-helper.S delete mode 100644 src/soc/litex/florent/microwatt/crt0.S rename src/soc/litex/{florent => florent_old}/Makefile (100%) rename src/soc/litex/{florent => florent_old}/README.txt (100%) rename src/soc/litex/{florent => florent_old}/SPBlock_512W64B8W.v (100%) rename src/soc/litex/{florent => florent_old}/idcode_test.svf (100%) rename src/soc/litex/{florent => florent_old}/idcode_test2.svf (100%) rename src/soc/litex/{florent => florent_old}/libresoc/__init__.py (100%) rename src/soc/litex/{ => florent_old/libresoc}/boot-helper.S (100%) rename src/soc/litex/{florent => florent_old}/libresoc/core.py (100%) rename src/soc/litex/{ => florent_old/libresoc}/crt0.S (100%) rename src/soc/litex/{florent => florent_old}/libresoc/irq.h (100%) rename src/soc/litex/{florent => florent_old}/libresoc/ls180.py (100%) rename src/soc/litex/{florent => florent_old}/libresoc/system.h (100%) rename src/soc/litex/{florent => florent_old}/ls180pins.txt (100%) rename src/soc/litex/{florent => florent_old}/ls180soc.py (100%) rename src/soc/litex/{florent => florent_old}/microwatt/__init__.py (100%) rename src/soc/litex/{florent/libresoc => florent_old/microwatt}/boot-helper.S (100%) rename src/soc/litex/{florent => florent_old}/microwatt/core.py (100%) rename src/soc/litex/{florent/libresoc => florent_old/microwatt}/crt0.S (100%) rename src/soc/litex/{florent => florent_old}/microwatt/irq.h (100%) rename src/soc/litex/{florent => florent_old}/microwatt/microwatt.v (100%) rename src/soc/litex/{florent => florent_old}/microwatt/system.h (100%) rename src/soc/litex/{florent => florent_old}/openocd.cfg (100%) rename src/soc/litex/{florent => florent_old}/sim.py (100%) rename src/soc/litex/{florent => florent_old}/versa_ecp5.py (100%) delete mode 100644 src/soc/litex/irq.h delete mode 100644 src/soc/litex/sim.py delete mode 100644 src/soc/litex/system.h diff --git a/.gitmodules b/.gitmodules index b03ac661..c1d0163c 100644 --- a/.gitmodules +++ b/.gitmodules @@ -8,3 +8,6 @@ [submodule "libreriscv"] path = libreriscv url = https://git.libre-soc.org/git/libreriscv.git +[submodule "src/soc/litex/florent"] + path = src/soc/litex/florent + url = https://git.libre-soc.org/git/libresoc-litex.git diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py deleted file mode 100644 index d391eb70..00000000 --- a/src/soc/litex/core.py +++ /dev/null @@ -1,143 +0,0 @@ -# Copyright (c) 2018 Jean-François Nguyen -# Copyright (c) 2018-2019 Florent Kermarrec -# License: BSD - -import os -import subprocess - -from migen import ClockSignal, ResetSignal, Signal, Instance, Cat - -from litex import get_data_mod -from litex.soc.interconnect import wishbone -from litex.soc.cores.cpu import CPU - -CPU_VARIANTS = ["standard"] - - -class LibreSOC(CPU): - name = "libre_soc" - human_name = "Libre-SOC" - variants = CPU_VARIANTS - data_width = 64 - endianness = "little" - gcc_triple = ("powerpc64le-linux", "powerpc64le-linux-gnu") - linker_output_format = "elf64-powerpcle" - nop = "nop" - io_regions = {0xc0000000: 0x10000000} # origin, length - - @property - def mem_map(self): - return {"csr": 0xc0000000} - - @property - def gcc_flags(self): - flags = "-m64 " - flags += "-mabi=elfv2 " - flags += "-msoft-float " - flags += "-mno-string " - flags += "-mno-multiple " - flags += "-mno-vsx " - flags += "-mno-altivec " - flags += "-mlittle-endian " - flags += "-mstrict-align " - flags += "-fno-stack-protector " - flags += "-D__microwatt__ " - return flags - - def __init__(self, platform, variant="standard"): - self.platform = platform - self.variant = variant - self.reset = Signal() - self.interrupt = Signal(32) - - self.pc = Signal(64) # new program counter - self.pc_ok = Signal() # change PC - self.core_start = Signal() # stop the core - self.core_stop = Signal() # start the core - self.bigendian = Signal() # set to 1 for bigendian - self.core_halted = Signal() # core is halted - self.core_busy = Signal() # core is running (busy) - - # instruction and data bus: 64-bit, 48 bit addressing - # sigh self.ibus = wishbone.Interface(data_width=32, adr_width=48) - self.ibus = wishbone.Interface(data_width=64, adr_width=48) - self.dbus = wishbone.Interface(data_width=64, adr_width=48) - - self.periph_buses = [self.ibus, self.dbus] - self.memory_buses = [] - - # TODO: create variants - - # # # - - self.cpu_params = dict( - # clock / reset - i_clk=ClockSignal(), - i_rst=ResetSignal() | self.reset, - - # TODO interrupts - #i_timer_interrupt = 0, - #i_software_interrupt = 0, - #i_external_interrupt = self.interrupt, - - # ibus - o_ibus__stb = self.ibus.stb, - o_ibus__cyc = self.ibus.cyc, - o_ibus__cti = self.ibus.cti, - o_ibus__bte = self.ibus.bte, - o_ibus__we = self.ibus.we, - # sigh o_ibus__adr = self.ibus.adr, # for 32-bit - o_ibus__adr = Cat(Signal(3), self.ibus.adr), # 64-bit - o_ibus__dat_w = self.ibus.dat_w, - o_ibus__sel = self.ibus.sel, - i_ibus__ack = self.ibus.ack, - i_ibus__err = self.ibus.err, - i_ibus__dat_r = self.ibus.dat_r, - - # dbus - o_dbus__stb = self.dbus.stb, - o_dbus__cyc = self.dbus.cyc, - o_dbus__cti = self.dbus.cti, - o_dbus__bte = self.dbus.bte, - o_dbus__we = self.dbus.we, - o_dbus__adr = Cat(Signal(3), self.dbus.adr), # 64-bit - o_dbus__dat_w = self.dbus.dat_w, - o_dbus__sel = self.dbus.sel, - i_dbus__ack = self.dbus.ack, - i_dbus__err = self.dbus.err, - i_dbus__dat_r = self.dbus.dat_r, - - # monitoring / debugging - i_go_insn_i = 1, # set to "always running" - i_pc_i = self.pc, - i_pc_i_ok = self.pc_ok, - i_core_start_i = self.core_start, - i_core_stop_i = self.core_stop, - i_core_bigendian_i = self.bigendian, - o_halted_o = self.core_halted, - o_busy_o = self.core_busy - ) - - def set_reset_address(self, reset_address): - assert not hasattr(self, "reset_address") - self.reset_address = reset_address - assert reset_address == 0x00000000 - - @staticmethod - def elaborate(verilog_filename): - cli_params = [] - #sdir = get_data_mod("cpu", "libre_soc").data_location - sdir = "./simple" - if subprocess.call(["python3", os.path.join(sdir, "issuer_verilog.py"), - *cli_params, verilog_filename], - ): - raise OSError("Unable to elaborate Libre-SOC CPU, " - "please check your nMigen/Yosys install") - - def do_finalize(self): - verilog_filename = os.path.join(self.platform.output_dir, - "gateware", "libre-soc.v") - self.elaborate(verilog_filename=verilog_filename) - self.platform.add_source(verilog_filename) - self.specials += Instance("test_issuer", **self.cpu_params) - diff --git a/src/soc/litex/florent b/src/soc/litex/florent new file mode 160000 index 00000000..c2808c90 --- /dev/null +++ b/src/soc/litex/florent @@ -0,0 +1 @@ +Subproject commit c2808c908523d44211057913b68c3e24b8bf74bf diff --git a/src/soc/litex/florent/microwatt/boot-helper.S b/src/soc/litex/florent/microwatt/boot-helper.S deleted file mode 100644 index 8dc226df..00000000 --- a/src/soc/litex/florent/microwatt/boot-helper.S +++ /dev/null @@ -1,4 +0,0 @@ -.section .text, "ax", @progbits -.global boot_helper -boot_helper: - nop # FIXME diff --git a/src/soc/litex/florent/microwatt/crt0.S b/src/soc/litex/florent/microwatt/crt0.S deleted file mode 100644 index e03ac0bb..00000000 --- a/src/soc/litex/florent/microwatt/crt0.S +++ /dev/null @@ -1,93 +0,0 @@ -/* Copyright 2013-2014 IBM Corp. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - * implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#define FIXUP_ENDIAN \ - tdi 0,0,0x48; /* Reverse endian of b . + 8 */ \ - b 191f; /* Skip trampoline if endian is good */ \ - .long 0xa600607d; /* mfmsr r11 */ \ - .long 0x01006b69; /* xori r11,r11,1 */ \ - .long 0x05009f42; /* bcl 20,31,$+4 */ \ - .long 0xa602487d; /* mflr r10 */ \ - .long 0x14004a39; /* addi r10,r10,20 */ \ - .long 0xa64b5a7d; /* mthsrr0 r10 */ \ - .long 0xa64b7b7d; /* mthsrr1 r11 */ \ - .long 0x2402004c; /* hrfid */ \ -191: - - -/* Load an immediate 64-bit value into a register */ -#define LOAD_IMM64(r, e) \ - lis r,(e)@highest; \ - ori r,r,(e)@higher; \ - rldicr r,r, 32, 31; \ - oris r,r, (e)@h; \ - ori r,r, (e)@l; - - . = 0 -.global _start -_start: - FIXUP_ENDIAN - - /* setup stack */ - LOAD_IMM64(%r1, _fstack - 0x100) - LOAD_IMM64(%r12, main) - mtctr %r12, - bctrl - b . - -#define EXCEPTION(nr) \ - .= nr; \ - b . - - /* More exception stubs */ - EXCEPTION(0x100) - EXCEPTION(0x200) - EXCEPTION(0x300) - EXCEPTION(0x380) - EXCEPTION(0x400) - EXCEPTION(0x480) - EXCEPTION(0x500) - EXCEPTION(0x600) - EXCEPTION(0x700) - EXCEPTION(0x800) - EXCEPTION(0x900) - EXCEPTION(0x980) - EXCEPTION(0xa00) - EXCEPTION(0xb00) - EXCEPTION(0xc00) - EXCEPTION(0xd00) - EXCEPTION(0xe00) - EXCEPTION(0xe20) - EXCEPTION(0xe40) - EXCEPTION(0xe60) - EXCEPTION(0xe80) - EXCEPTION(0xf00) - EXCEPTION(0xf20) - EXCEPTION(0xf40) - EXCEPTION(0xf60) - EXCEPTION(0xf80) -#if 0 - EXCEPTION(0x1000) - EXCEPTION(0x1100) - EXCEPTION(0x1200) - EXCEPTION(0x1300) - EXCEPTION(0x1400) - EXCEPTION(0x1500) - EXCEPTION(0x1600) -#endif - - .text - diff --git a/src/soc/litex/florent/Makefile b/src/soc/litex/florent_old/Makefile similarity index 100% rename from src/soc/litex/florent/Makefile rename to src/soc/litex/florent_old/Makefile diff --git a/src/soc/litex/florent/README.txt b/src/soc/litex/florent_old/README.txt similarity index 100% rename from src/soc/litex/florent/README.txt rename to src/soc/litex/florent_old/README.txt diff --git a/src/soc/litex/florent/SPBlock_512W64B8W.v b/src/soc/litex/florent_old/SPBlock_512W64B8W.v similarity index 100% rename from src/soc/litex/florent/SPBlock_512W64B8W.v rename to src/soc/litex/florent_old/SPBlock_512W64B8W.v diff --git a/src/soc/litex/florent/idcode_test.svf b/src/soc/litex/florent_old/idcode_test.svf similarity index 100% rename from src/soc/litex/florent/idcode_test.svf rename to src/soc/litex/florent_old/idcode_test.svf diff --git a/src/soc/litex/florent/idcode_test2.svf b/src/soc/litex/florent_old/idcode_test2.svf similarity index 100% rename from src/soc/litex/florent/idcode_test2.svf rename to src/soc/litex/florent_old/idcode_test2.svf diff --git a/src/soc/litex/florent/libresoc/__init__.py b/src/soc/litex/florent_old/libresoc/__init__.py similarity index 100% rename from src/soc/litex/florent/libresoc/__init__.py rename to src/soc/litex/florent_old/libresoc/__init__.py diff --git a/src/soc/litex/boot-helper.S b/src/soc/litex/florent_old/libresoc/boot-helper.S similarity index 100% rename from src/soc/litex/boot-helper.S rename to src/soc/litex/florent_old/libresoc/boot-helper.S diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent_old/libresoc/core.py similarity index 100% rename from src/soc/litex/florent/libresoc/core.py rename to src/soc/litex/florent_old/libresoc/core.py diff --git a/src/soc/litex/crt0.S b/src/soc/litex/florent_old/libresoc/crt0.S similarity index 100% rename from src/soc/litex/crt0.S rename to src/soc/litex/florent_old/libresoc/crt0.S diff --git a/src/soc/litex/florent/libresoc/irq.h b/src/soc/litex/florent_old/libresoc/irq.h similarity index 100% rename from src/soc/litex/florent/libresoc/irq.h rename to src/soc/litex/florent_old/libresoc/irq.h diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent_old/libresoc/ls180.py similarity index 100% rename from src/soc/litex/florent/libresoc/ls180.py rename to src/soc/litex/florent_old/libresoc/ls180.py diff --git a/src/soc/litex/florent/libresoc/system.h b/src/soc/litex/florent_old/libresoc/system.h similarity index 100% rename from src/soc/litex/florent/libresoc/system.h rename to src/soc/litex/florent_old/libresoc/system.h diff --git a/src/soc/litex/florent/ls180pins.txt b/src/soc/litex/florent_old/ls180pins.txt similarity index 100% rename from src/soc/litex/florent/ls180pins.txt rename to src/soc/litex/florent_old/ls180pins.txt diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent_old/ls180soc.py similarity index 100% rename from src/soc/litex/florent/ls180soc.py rename to src/soc/litex/florent_old/ls180soc.py diff --git a/src/soc/litex/florent/microwatt/__init__.py b/src/soc/litex/florent_old/microwatt/__init__.py similarity index 100% rename from src/soc/litex/florent/microwatt/__init__.py rename to src/soc/litex/florent_old/microwatt/__init__.py diff --git a/src/soc/litex/florent/libresoc/boot-helper.S b/src/soc/litex/florent_old/microwatt/boot-helper.S similarity index 100% rename from src/soc/litex/florent/libresoc/boot-helper.S rename to src/soc/litex/florent_old/microwatt/boot-helper.S diff --git a/src/soc/litex/florent/microwatt/core.py b/src/soc/litex/florent_old/microwatt/core.py similarity index 100% rename from src/soc/litex/florent/microwatt/core.py rename to src/soc/litex/florent_old/microwatt/core.py diff --git a/src/soc/litex/florent/libresoc/crt0.S b/src/soc/litex/florent_old/microwatt/crt0.S similarity index 100% rename from src/soc/litex/florent/libresoc/crt0.S rename to src/soc/litex/florent_old/microwatt/crt0.S diff --git a/src/soc/litex/florent/microwatt/irq.h b/src/soc/litex/florent_old/microwatt/irq.h similarity index 100% rename from src/soc/litex/florent/microwatt/irq.h rename to src/soc/litex/florent_old/microwatt/irq.h diff --git a/src/soc/litex/florent/microwatt/microwatt.v b/src/soc/litex/florent_old/microwatt/microwatt.v similarity index 100% rename from src/soc/litex/florent/microwatt/microwatt.v rename to src/soc/litex/florent_old/microwatt/microwatt.v diff --git a/src/soc/litex/florent/microwatt/system.h b/src/soc/litex/florent_old/microwatt/system.h similarity index 100% rename from src/soc/litex/florent/microwatt/system.h rename to src/soc/litex/florent_old/microwatt/system.h diff --git a/src/soc/litex/florent/openocd.cfg b/src/soc/litex/florent_old/openocd.cfg similarity index 100% rename from src/soc/litex/florent/openocd.cfg rename to src/soc/litex/florent_old/openocd.cfg diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent_old/sim.py similarity index 100% rename from src/soc/litex/florent/sim.py rename to src/soc/litex/florent_old/sim.py diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent_old/versa_ecp5.py similarity index 100% rename from src/soc/litex/florent/versa_ecp5.py rename to src/soc/litex/florent_old/versa_ecp5.py diff --git a/src/soc/litex/irq.h b/src/soc/litex/irq.h deleted file mode 100644 index 35beaed2..00000000 --- a/src/soc/litex/irq.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __IRQ_H -#define __IRQ_H - -static inline unsigned int irq_getie(void) -{ - return 0; -} - -static inline void irq_setie(unsigned int ie) -{ - /*if(ie) csrs(); else csrc();*/ -} - -static inline unsigned int irq_getmask(void) -{ - unsigned int mask = 0; - //asm volatile ("csrr %0, %1" : "=r"(mask) : "i"(CSR_IRQ_MASK)); - return mask; -} - -static inline void irq_setmask(unsigned int mask) -{ - //asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); -} - -static inline unsigned int irq_pending(void) -{ - unsigned int pending = 0; - //asm volatile ("csrr %0, %1" : "=r"(pending) : "i"(CSR_IRQ_PENDING)); - return pending; -} - -#endif /* __IRQ_H */ diff --git a/src/soc/litex/sim.py b/src/soc/litex/sim.py deleted file mode 100644 index a9935353..00000000 --- a/src/soc/litex/sim.py +++ /dev/null @@ -1,165 +0,0 @@ -#!/usr/bin/env python3 - -# This file is Copyright (c) 2020 Florent Kermarrec -# This file is Copyright (c) 2020 Dolu1990 -# License: BSD - -import os -import argparse - -from litex.build.generic_platform import Pins, Subsignal -from litex.build.sim import SimPlatform -from litex.build.io import CRG -from litex.build.sim.config import SimConfig - -from litex.soc.integration.soc import SoCRegion -from litex.soc.integration.soc_core import SoCCore -from litex.soc.integration.common import get_mem_data -from litex.soc.integration.builder import Builder - -from litedram.modules import IS42S16160, MT41K128M16 -from litedram.phy.model import SDRAMPHYModel -from litedram.core.controller import ControllerSettings - -from litex.tools.litex_sim import get_sdram_phy_settings - -from soc.litex.core import LibreSOC - -# IOs ------------------------------------------------------------------ - -_io = [ - ("sys_clk", 0, Pins(1)), - ("sys_rst", 0, Pins(1)), - ("serial", 0, - Subsignal("source_valid", Pins(1)), - Subsignal("source_ready", Pins(1)), - Subsignal("source_data", Pins(8)), - - Subsignal("sink_valid", Pins(1)), - Subsignal("sink_ready", Pins(1)), - Subsignal("sink_data", Pins(8)), - ), -] - -# Platform -------------------------------------------------------------- - -class Platform(SimPlatform): - def __init__(self): - SimPlatform.__init__(self, "SIM", _io) - -# SoCSMP ---------------------------------------------------------------- - -class SoCSMP(SoCCore): - def __init__(self, cpu_variant, init_memories=False, with_sdcard=False): - platform = Platform() - sys_clk_freq = int(100e6) - - sdram_init = [] - if init_memories: - sdram_init = get_mem_data({ - "images/fw_jump.bin": "0x00f00000", - "images/Image": "0x00000000", - "images/dtb" : "0x00ef0000", - "images/rootfs.cpio": "0x01000000", - }, "little") - - # SoCCore -------------------------------------------------------- - SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, - cpu_type = "microwatt", # XXX use microwatt - cpu_variant = cpu_variant, - cpu_cls = LibreSOC, - bus_data_width = 32, # XXX TODO 64 bit wishbone data bus - uart_name = "sim", - integrated_rom_size = 0x8000, - integrated_main_ram_size = 0x00000000) - - self.platform.name = "sim" - self.add_constant("SIM") - - # CRG ------------------------------------------------------- - self.submodules.crg = CRG(platform.request("sys_clk")) - - # SDRAM ---------------------------------------------------------- - if False: - phy_settings = get_sdram_phy_settings( - #memtype = "DDR3", - memtype = "SDR", - data_width = 16, - clk_freq = 100e6) - self.submodules.sdrphy = SDRAMPHYModel( - #module = MT41K128M16(100e6, "1:4"), - module = IS42S16160(100e6, "1:4"), - settings = phy_settings, - clk_freq = 100e6, - init = sdram_init) - self.add_sdram("sdram", - phy = self.sdrphy, - #module = MT41K128M16(100e6, "1:4"), - module = IS42S16160(100e6, "1:4"), - origin = self.mem_map["main_ram"], - #controller_settings = ControllerSettings( - # cmd_buffer_buffered = False, - # with_auto_precharge = True - #) - ) - if init_memories: - addr = 0x40f00000 - self.add_constant("MEMTEST_BUS_SIZE", 0) # Skip test if memory is - self.add_constant("MEMTEST_ADDR_SIZE", 0) # initialized to avoid - self.add_constant("MEMTEST_DATA_SIZE", 0) # corrumpting the content. - self.add_constant("ROM_BOOT_ADDRESS", addr) # Jump to fw_jump.bin - else: - self.add_constant("MEMTEST_BUS_SIZE", 4096//64) - self.add_constant("MEMTEST_ADDR_SIZE", 4096//256) - self.add_constant("MEMTEST_DATA_SIZE", 4096//32) - - # SDCard ----------------------------------------------------- - if with_sdcard: - self.add_sdcard("sdcard", use_emulator=True) - -# Build ----------------------------------------------------------------- - -def main(): - parser = argparse.ArgumentParser( - description="Linux on LiteX-LibreSOC Simulation") - parser.add_argument("--cpu-variant", default="standard", - help="Select CPU netlist variant") - parser.add_argument("--sdram-init", action="store_true", - help="Init SDRAM with Linux images") - parser.add_argument("--with-sdcard", action="store_true", - help="Enable SDCard support") - parser.add_argument("--trace", action="store_true", - help="Enable VCD tracing") - parser.add_argument("--trace-start", default=0, - help="Cycle to start VCD tracing") - parser.add_argument("--trace-end", default=-1, - help="Cycle to end VCD tracing") - parser.add_argument("--opt-level", default="O3", - help="Compilation optimization level") - args = parser.parse_args() - - sim_config = SimConfig(default_clk="sys_clk") - sim_config.add_module("serial2console", "serial") - - for i in range(2): - to_run = (i != 0) # first build (i=0), then run (i=1) - soc = SoCSMP(args.cpu_variant, args.sdram_init and to_run, - args.with_sdcard) - builder = Builder(soc, - compile_gateware = to_run, - csr_json = "build/sim/csr.json") - builder.build(sim_config=sim_config, - run = to_run, - opt_level = args.opt_level, - trace = args.trace, - trace_start = int(args.trace_start), - trace_end = int(args.trace_end), - trace_fst = 0) - os.chdir("../") - #if not to_run: - # os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME - # os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME - # os.system("cp verilog/*.bin build/sim/gateware/") - -if __name__ == "__main__": - main() diff --git a/src/soc/litex/system.h b/src/soc/litex/system.h deleted file mode 100644 index 941dc564..00000000 --- a/src/soc/litex/system.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __SYSTEM_H -#define __SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -__attribute__((unused)) static void flush_cpu_icache(void){}; /* FIXME: do something useful here! */ -__attribute__((unused)) static void flush_cpu_dcache(void){}; /* FIXME: do something useful here! */ -void flush_l2_cache(void); - -void busy_wait(unsigned int ms); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_H */ -- 2.30.2