From 9784ecefb8a9b0e8e7aeae4c92fc1a622ac45325 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Wed, 17 Mar 2021 20:54:28 +0000
Subject: [PATCH]

---
 openpower/sv/implementation.mdwn | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index aff1ad04f..0f54ff3bd 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -188,14 +188,23 @@ At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP sca
 
 ## Single and Twin Predication
 
-both CR and INT predication is needed, as well as zeroing in both
-
-* INT-based single: TODO
-* CR-based single:  TODO
-* INT-based twin:   TODO
-* CR-based twin:    TODO
-* Zeroing single:   TODO
-* Zeroing twin:     TODO
+both CR and INT predication is needed, as well as zeroing in both.
+the order is best done as follows:
+
+* INT-based single
+* CR-based single
+* srcstep+dststep
+* INT-based twin
+* CR-based twin
+* Zeroing single
+* Zeroing twin
+
+Best done as a FSM that "advances" srcstep and dststep over the
+zeros in their respective predicate masks, *including* when the
+src and dest predicate mask is "All 1s".
+
+Bear in mind that srcstep+deststep are a form of back-to-back
+VGATHER+VSCATTER
 
 Progress:
 
-- 
2.30.2