From 9b8e44c1e4da1e806b0971732f451c32414927c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 31 Jan 2022 14:59:45 +0000 Subject: [PATCH] remove combinatorial loop from MultiCompUnit actually not a loop due to an SRLatch but synth tools still think it is --- src/soc/experiment/compalu_multi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 1c521c4b..d33be619 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -198,7 +198,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): # ALU only proceeds when all src are ready. rd_rel_o is delayed # so combine it with go_rd_i. if all bits are set we're good all_rd = Signal(reset_less=True) - m.d.comb += all_rd.eq(self.busy_o & rok_l.q & # XXX LOOP + m.d.comb += all_rd.eq(self.busy_o & # rok_l.q & # XXX LOOP (((~self.rd.rel_o) | self.rd.go_i).all())) # generate read-done pulse @@ -355,7 +355,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.submodules.alu_l = alu_l = SRLatch(False, name="alu") m.d.comb += self.alu.n.i_ready.eq(alu_l.q) m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q) - m.d.comb += alu_l.s.eq(all_rd_pulse) + m.d.comb += alu_l.s.eq(all_rd_pulse) # XXX LOOP # ----- # outputs -- 2.30.2