From 9e3b7bdc5ab045e2a526bbbbbb26475b6ef91468 Mon Sep 17 00:00:00 2001 From: Brian Campbell Date: Mon, 19 Dec 2016 17:54:19 +0000 Subject: [PATCH] Fix gdb protocol register read of S0 --- riscv/gdbserver.cc | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 3e68872..c4e0fef 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -592,12 +592,16 @@ class register_read_op_t : public operation_t switch (step) { case 0: if (reg >= REG_XPR0 && reg <= REG_XPR31) { + unsigned int i = 0; + if (reg == S0) { + gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH)); + } if (gs.xlen == 32) { - gs.dr_write32(0, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); + gs.dr_write32(i++, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); } else { - gs.dr_write32(0, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); + gs.dr_write32(i++, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16)); } - gs.dr_write_jump(1); + gs.dr_write_jump(i); } else if (reg == REG_PC) { gs.start_packet(); if (gs.xlen == 32) { -- 2.30.2