From 9f2e888b851c4fd5f1731aec6bd88bfa9efecf86 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 24 May 2018 13:28:52 +0100 Subject: [PATCH] add slide --- simple_v_extension/simple_v_chennai_2018.tex | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index e76e62ea4..ef26dc67a 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -361,15 +361,16 @@ for (int i = 0; i < VL; ++i) \frame{\frametitle{Under consideration} \begin{itemize} - \item Is C.FNE actually needed?\vspace{10pt} - \item Can VSELECT be removed? (it's really complex)\vspace{10pt} - \item Can CLIP be done as a CSR (mode, like elwidth)\vspace{10pt} - \item SIMD saturation (etc.) also set as a mode?\vspace{10pt} + \item Is C.FNE actually needed? Should it be added if it is? + \item Is detection of all-scalar ops ok (without slowing pipeline)? + \item Can VSELECT be removed? (it's really complex) + \item Can CLIP be done as a CSR (mode, like elwidth) + \item SIMD saturation (etc.) also set as a mode? \item C.MV src predication no different from dest predication\\ - What to do? Make one have different meaning?\vspace{10pt} + What to do? Make one have different meaning? \item 8/16-bit ops is it worthwhile adding a "start offset"? \\ (a bit like misaligned addressing... for registers)\\ - or just use predication to skip start?\vspace{10pt} + or just use predication to skip start? \end{itemize} } -- 2.30.2