From a06091861c23d5154d750137f5ff3a819a9fa283 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 27 Nov 2017 14:28:29 -0800 Subject: [PATCH] Rename sptbr to satp --- riscv/encoding.h | 32 ++++++++++++++++---------------- riscv/mmu.cc | 2 +- riscv/mmu.h | 20 ++++++++++---------- riscv/processor.cc | 16 ++++++++-------- riscv/processor.h | 2 +- 5 files changed, 36 insertions(+), 36 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 8ec1345..1173fe5 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -113,19 +113,19 @@ #define PRV_H 2 #define PRV_M 3 -#define SPTBR32_MODE 0x80000000 -#define SPTBR32_ASID 0x7FC00000 -#define SPTBR32_PPN 0x003FFFFF -#define SPTBR64_MODE 0xF000000000000000 -#define SPTBR64_ASID 0x0FFFF00000000000 -#define SPTBR64_PPN 0x00000FFFFFFFFFFF +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7FC00000 +#define SATP32_PPN 0x003FFFFF +#define SATP64_MODE 0xF000000000000000 +#define SATP64_ASID 0x0FFFF00000000000 +#define SATP64_PPN 0x00000FFFFFFFFFFF -#define SPTBR_MODE_OFF 0 -#define SPTBR_MODE_SV32 1 -#define SPTBR_MODE_SV39 8 -#define SPTBR_MODE_SV48 9 -#define SPTBR_MODE_SV57 10 -#define SPTBR_MODE_SV64 11 +#define SATP_MODE_OFF 0 +#define SATP_MODE_SV32 1 +#define SATP_MODE_SV39 8 +#define SATP_MODE_SV48 9 +#define SATP_MODE_SV57 10 +#define SATP_MODE_SV64 11 #define PMP_R 0x01 #define PMP_W 0x02 @@ -177,12 +177,12 @@ # define MSTATUS_SD MSTATUS64_SD # define SSTATUS_SD SSTATUS64_SD # define RISCV_PGLEVEL_BITS 9 -# define SPTBR_MODE SPTBR64_MODE +# define SATP_MODE SATP64_MODE #else # define MSTATUS_SD MSTATUS32_SD # define SSTATUS_SD SSTATUS32_SD # define RISCV_PGLEVEL_BITS 10 -# define SPTBR_MODE SPTBR32_MODE +# define SATP_MODE SATP32_MODE #endif #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) @@ -792,7 +792,7 @@ #define CSR_SCAUSE 0x142 #define CSR_SBADADDR 0x143 #define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 +#define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 @@ -1284,7 +1284,7 @@ DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(medeleg, CSR_MEDELEG) diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 54b5b1d..5f054db 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -159,7 +159,7 @@ tlb_entry_t mmu_t::refill_tlb(reg_t vaddr, reg_t paddr, char* host_addr, access_ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode) { - vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->sptbr); + vm_info vm = decode_vm_info(proc->max_xlen, mode, proc->get_state()->satp); if (vm.levels == 0) return addr & ((reg_t(2) << (proc->xlen-1))-1); // zero-extend from xlen diff --git a/riscv/mmu.h b/riscv/mmu.h index 7d6ea88..e39cd94 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -320,23 +320,23 @@ struct vm_info { reg_t ptbase; }; -inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t sptbr) +inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t satp) { if (prv == PRV_M) { return {0, 0, 0, 0}; } else if (prv <= PRV_S && xlen == 32) { - switch (get_field(sptbr, SPTBR32_MODE)) { - case SPTBR_MODE_OFF: return {0, 0, 0, 0}; - case SPTBR_MODE_SV32: return {2, 10, 4, (sptbr & SPTBR32_PPN) << PGSHIFT}; + switch (get_field(satp, SATP32_MODE)) { + case SATP_MODE_OFF: return {0, 0, 0, 0}; + case SATP_MODE_SV32: return {2, 10, 4, (satp & SATP32_PPN) << PGSHIFT}; default: abort(); } } else if (prv <= PRV_S && xlen == 64) { - switch (get_field(sptbr, SPTBR64_MODE)) { - case SPTBR_MODE_OFF: return {0, 0, 0, 0}; - case SPTBR_MODE_SV39: return {3, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT}; - case SPTBR_MODE_SV48: return {4, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT}; - case SPTBR_MODE_SV57: return {5, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT}; - case SPTBR_MODE_SV64: return {6, 9, 8, (sptbr & SPTBR64_PPN) << PGSHIFT}; + switch (get_field(satp, SATP64_MODE)) { + case SATP_MODE_OFF: return {0, 0, 0, 0}; + case SATP_MODE_SV39: return {3, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV48: return {4, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV57: return {5, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; + case SATP_MODE_SV64: return {6, 9, 8, (satp & SATP64_PPN) << PGSHIFT}; default: abort(); } } else { diff --git a/riscv/processor.cc b/riscv/processor.cc index 564b34f..5f095c3 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -425,14 +425,14 @@ void processor_t::set_csr(int which, reg_t val) case CSR_SIE: return set_csr(CSR_MIE, (state.mie & ~state.mideleg) | (val & state.mideleg)); - case CSR_SPTBR: { + case CSR_SATP: { mmu->flush_tlb(); if (max_xlen == 32) - state.sptbr = val & (SPTBR32_PPN | SPTBR32_MODE); - if (max_xlen == 64 && (get_field(val, SPTBR64_MODE) == SPTBR_MODE_OFF || - get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV39 || - get_field(val, SPTBR64_MODE) == SPTBR_MODE_SV48)) - state.sptbr = val & (SPTBR64_PPN | SPTBR64_MODE); + state.satp = val & (SATP32_PPN | SATP32_MODE); + if (max_xlen == 64 && (get_field(val, SATP64_MODE) == SATP_MODE_OFF || + get_field(val, SATP64_MODE) == SATP_MODE_SV39 || + get_field(val, SATP64_MODE) == SATP_MODE_SV48)) + state.satp = val & (SATP64_PPN | SATP64_MODE); break; } case CSR_SEPC: state.sepc = val; break; @@ -590,10 +590,10 @@ reg_t processor_t::get_csr(int which) if (max_xlen > xlen) return state.scause | ((state.scause >> (max_xlen-1)) << (xlen-1)); return state.scause; - case CSR_SPTBR: + case CSR_SATP: if (get_field(state.mstatus, MSTATUS_TVM)) require_privilege(PRV_M); - return state.sptbr; + return state.satp; case CSR_SSCRATCH: return state.sscratch; case CSR_MSTATUS: return state.mstatus; case CSR_MIP: return state.mip; diff --git a/riscv/processor.h b/riscv/processor.h index 87cb6a4..f37fb59 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -112,7 +112,7 @@ struct state_t reg_t sbadaddr; reg_t sscratch; reg_t stvec; - reg_t sptbr; + reg_t satp; reg_t scause; reg_t dpc; reg_t dscratch; -- 2.30.2