From a24744139025cce94eab543241c12d27a37b7f85 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Thu, 7 Jan 2021 18:25:48 +0100 Subject: [PATCH] set initial_sprs, cleanup mfspr testprog --- src/soc/fu/mmu/test/test_pipe_caller.py | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index 71aae015..e45b3065 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -77,15 +77,14 @@ class MMUTestCase(TestAccumulatorBase): def case_mfspr_after_invalid_load(self): lst = [ # TODO -- set SPR on both sinulator and port interface - "mfspr 1, 18", # DSISR to reg 1 -- KeyError: 2 in simulator - "mfspr 2, 19", # DAR to reg 2 -- with key = spr_dict[key].SPR + "mfspr 1, 18", # DSISR to reg 1 + "mfspr 2, 19", # DAR to reg 2 # TODO -- verify returned sprvals ] initial_regs = [0] * 32 - initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234, - 'XER': 0xe00c0000} + initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321} self.add_case(Program(lst, bigendian), initial_regs, initial_sprs) -- 2.30.2