From a3bb5abf6b571a77b7922eff0e93d0d3e54171a9 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Sun, 7 Mar 2021 17:39:23 +0100 Subject: [PATCH] RADIX: implement memassign and call --- src/soc/decoder/isa/caller.py | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 0925915b..c8df6e62 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -228,6 +228,12 @@ class RADIX: self.pgtbl3 = 0 self.pt3_valid = False + def __call__(self,*args, **kwargs): + print("TODO: implement RADIX.__call__()") + print(args) + print(kwargs) + return None + def ld(self, address, width=8, swap=True, check_in_mem=False): print("RADIX: ld from addr 0x%x width %d" % (address, width)) @@ -241,7 +247,10 @@ class RADIX: # use pte to caclculate phys address (addr) return self.mem.st(addr, v, width, swap) - # def memassign(self, addr, sz, val): + def memassign(self, addr, sz, val): + print("memassign", addr, sz, val) + self.st(addr.value, val.value, sz, swap=False) + def _next_level(self): return True ## DSISR_R_BADCONFIG -- 2.30.2