From aa33c1b9de05e7ff3fbd5ce577f5917f3d142d32 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 20 Feb 2021 23:15:06 +0000 Subject: [PATCH] add CR1 to DecodeCRIn/Out --- src/soc/decoder/power_decoder2.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 85f7b32d..05914987 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -681,6 +681,9 @@ class DecodeCRIn(Elaboratable): with m.Case(CRInSel.CR0): comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(1) + with m.Case(CRInSel.CR1): + comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering) + comb += self.cr_bitfield.ok.eq(1) with m.Case(CRInSel.BI): comb += self.cr_bitfield.data.eq(self.dec.BI[2:5]) comb += self.cr_bitfield.ok.eq(1) @@ -743,6 +746,9 @@ class DecodeCROut(Elaboratable): with m.Case(CROutSel.CR0): comb += self.cr_bitfield.data.eq(0) # CR0 (MSB0 numbering) comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1 + with m.Case(CROutSel.CR1): + comb += self.cr_bitfield.data.eq(1) # CR1 (MSB0 numbering) + comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1 with m.Case(CROutSel.BF): comb += self.cr_bitfield.data.eq(self.dec.FormX.BF) comb += self.cr_bitfield.ok.eq(1) -- 2.30.2