From ab0309b710a191b1a8e3051a59b5ab298e75d601 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 15 Jun 2019 14:10:03 +0100 Subject: [PATCH] rename match to nomatch, connect ld_i and st_i --- src/experiment/score6600.py | 18 +++++++++++++----- src/scoreboard/addr_match.py | 11 ++++++++--- src/scoreboard/mdm.py | 2 +- src/scoreboard/memfu.py | 4 ++-- 4 files changed, 24 insertions(+), 11 deletions(-) diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index e6918133..e8b1e8bb 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -540,9 +540,15 @@ class Scoreboard(Elaboratable): #--------- # Memory Function Unit #--------- + reset_b = Signal(cul.n_units, reset_less=True) + sync += reset_b.eq(cul.go_st_i | cul.go_wr_i | cul.go_die_i) comb += memfus.fn_issue_i.eq(cul.issue_i) # Comp Unit Issue -> Mem FUs - comb += memfus.addr_we_i.eq(cul.adr_rel_o) # Match enable on adr rel - comb += memfus.addr_rs_i.eq(~cul.busy_o) # Match disable on busy off + comb += memfus.addr_en_i.eq(cul.adr_rel_o) # Match enable on adr rel + comb += memfus.addr_rs_i.eq(reset_b) # reset same as LDSTCompUnit + with m.If(self.ls_oper_i[2]): # LD bit of operand + comb += memfus.ld_i.eq(cul.issue_i) + with m.If(self.ls_oper_i[3]): # ST bit of operand + comb += memfus.st_i.eq(cul.issue_i) # connect up address data comb += memfus.addrs_i[0].eq(cul.units[0].data_o) @@ -551,8 +557,10 @@ class Scoreboard(Elaboratable): # connect loadable / storable to go_ld/go_st. # XXX should only be done when the memory ld/st has actually happened! - #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_match_o) - #comb += cul.go_st_i.eq(memfus.storable_o & memfus.addr_match_o) + comb += memfus.go_ld_i.eq(memfus.loadable_o & memfus.addr_nomatch_o) + comb += memfus.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o) + #comb += cul.go_wr_i.eq(memfus.loadable_o & memfus.addr_nomatch_o) + comb += cul.go_st_i.eq(memfus.storable_o & memfus.addr_nomatch_o) #comb += cu.go_rd_i[0:n_intfus].eq(go_rd_o[0:n_intfus]) #comb += cu.go_wr_i[0:n_intfus].eq(go_wr_o[0:n_intfus]) @@ -1120,7 +1128,7 @@ def scoreboard_sim(dut, alusim): if True: # LD/ST test (with immediate) instrs.append( (1, 2, 2, 0x10, 1, 1, (0, 0)) ) - #instrs.append( (5, 6, 7, 0x10, 1, 1, (0, 0)) ) + #instrs.append( (1, 2, 7, 0x10, 1, 1, (0, 0)) ) if False: instrs.append( (1, 2, 2, 1, 1, 20, (0, 0)) ) diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py index bad7c78f..6c4f6832 100644 --- a/src/scoreboard/addr_match.py +++ b/src/scoreboard/addr_match.py @@ -48,7 +48,8 @@ class PartialAddrMatch(Elaboratable): self.addr_rs_i = Signal(n_adr) # address deactivated # output - self.addr_match_o = Array(Signal(n_adr, name="match_o") \ + self.addr_nomatch_o = Signal(n_adr, name="nomatch_o") + self.addr_nomatch_a_o = Array(Signal(n_adr, name="nomatch_array_o") \ for i in range(n_adr)) def elaborate(self, platform): @@ -71,6 +72,7 @@ class PartialAddrMatch(Elaboratable): latchregister(m, self.addrs_i[i], addrs_r[i], l.q[i]) # is there a clash, yes/no + matchgrp = [] for i in range(self.n_adr): nomatch = [] for j in range(self.n_adr): @@ -78,7 +80,9 @@ class PartialAddrMatch(Elaboratable): nomatch.append(Const(1)) # don't match against self! else: nomatch.append(addrs_r[i] != addrs_r[j]) - comb += self.addr_match_o[i].eq(Cat(*nomatch) & l.q) + matchgrp.append((~Cat(*nomatch)).bool()) # true if all matches fail + comb += self.addr_nomatch_o[i].eq(Cat(*nomatch) & l.q) + comb += self.addr_nomatch_o.eq((~Cat(*matchgrp)) & l.q) return m @@ -86,7 +90,8 @@ class PartialAddrMatch(Elaboratable): yield from self.addrs_i yield self.addr_we_i yield self.addr_en_i - yield from self.addr_match_o + yield from self.addr_nomatch_a_o + yield self.addr_nomatch_o def ports(self): return list(self) diff --git a/src/scoreboard/mdm.py b/src/scoreboard/mdm.py index 72ac9592..184931ef 100644 --- a/src/scoreboard/mdm.py +++ b/src/scoreboard/mdm.py @@ -10,7 +10,7 @@ class FUMemMatchMatrix(FURegDepMatrix, PartialAddrMatch): """ def __init__(self, n_fu, addrbitwid): PartialAddrMatch.__init__(self, n_fu, addrbitwid) - FURegDepMatrix.__init__(self, n_fu, n_fu, 1, self.addr_match_o) + FURegDepMatrix.__init__(self, n_fu, n_fu, 1, self.addr_nomatch_o) def elaborate(self, platform): m = Module() diff --git a/src/scoreboard/memfu.py b/src/scoreboard/memfu.py index 8173acec..857d96c9 100644 --- a/src/scoreboard/memfu.py +++ b/src/scoreboard/memfu.py @@ -23,7 +23,7 @@ class MemFunctionUnits(Elaboratable): self.loadable_o = Signal(n_ldsts, reset_less=True) self.storable_o = Signal(n_ldsts, reset_less=True) - #self.addr_match_o = Signal(n_ldsts, reset_less=True) + self.addr_nomatch_o = Signal(n_ldsts, reset_less=True) self.go_ld_i = Signal(n_ldsts, reset_less=True) self.go_st_i = Signal(n_ldsts, reset_less=True) @@ -76,7 +76,7 @@ class MemFunctionUnits(Elaboratable): comb += intfudeps.go_die_i.eq(self.go_die_i) comb += self.loadable_o.eq(intfudeps.readable_o) comb += self.storable_o.eq(intfudeps.writable_o) - #comb += self.addr_match_o.eq(intregdeps.addr_match_o) + comb += self.addr_nomatch_o.eq(intregdeps.addr_nomatch_o) # Connect function issue / arrays, and dest/src1/src2 comb += intregdeps.dest_i.eq(self.st_i) -- 2.30.2