From ab617dd705de21245fb8960e423e5331409cdd1b Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Thu, 31 Dec 2020 18:41:18 -0300 Subject: [PATCH] Implement and test NOP in the test ALU Change the output port from Signal to Data, to allow for the output to be masked-out. Specify a masked-out output in the NOP test case. --- src/soc/experiment/alu_hier.py | 16 ++++++++++------ src/soc/experiment/test/test_compalu_multi.py | 7 +++---- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index 39a4be95..8dbfa041 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -22,6 +22,7 @@ from nmutil.gtkw import write_gtkw from nmutil.sim_tmp_alternative import (Simulator, nmigen_sim_top_module, is_engine_pysim) +from soc.decoder.decode2execute1 import Data from soc.decoder.power_enums import MicrOp, Function, CryIn from soc.fu.alu.alu_input_record import CompALUOpSubset @@ -195,7 +196,7 @@ class ALU(Elaboratable): i.append(Signal(width, name="i2")) self.i = Array(i) self.a, self.b = i[0], i[1] - self.out = Array([Signal(width, name="alu_o")]) + self.out = Array([Data(width, name="alu_o")]) self.o = self.out[0] self.width = width # more "look like nmutil pipeline API" @@ -260,6 +261,9 @@ class ALU(Elaboratable): # hold the ALU result until ready_o is asserted alu_r = Signal(self.width) + # NOP doesn't output anything + with m.If(self.op.insn_type != MicrOp.OP_NOP): + m.d.comb += self.o.ok.eq(1) with m.If(alu_idle): with m.If(self.p.valid_i): @@ -303,10 +307,10 @@ class ALU(Elaboratable): # choose between zero-delay output, or registered with m.If(go_now): - m.d.comb += self.o.eq(sub.o) + m.d.comb += self.o.data.eq(sub.o) # only present the result at the last computation cycle with m.Elif(alu_done): - m.d.comb += self.o.eq(alu_r) + m.d.comb += self.o.data.eq(alu_r) return m @@ -314,7 +318,7 @@ class ALU(Elaboratable): yield from self.op.ports() yield self.a yield self.b - yield self.o + yield from self.o.ports() yield self.p.valid_i yield self.p.ready_o yield self.n.valid_o @@ -447,7 +451,7 @@ def run_op(dut, a, b, op, inv_a=0): yield # latch the result and lower read_i - result = yield dut.o + result = yield dut.o.data yield dut.n.ready_i.eq(0) return result @@ -525,7 +529,7 @@ def test_alu_parallel(): while not (yield dut.n.valid_o): yield # read result - result = yield dut.o + result = yield dut.o.data # negate ready_i # if receive is called again immediately afterwards, there will be no # visible transition (it will not be negated, after all) diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index ed97189d..0f5f6a7c 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -462,11 +462,10 @@ def scoreboard_sim(op): yield from op.issue([2, 0x80], MicrOp.OP_EXTSWSLI, [0xFF80], rdmaskn=[1, 0], src_delays=[1, 2], dest_delays=[1]) - # 0 (masked) + 0 (masked) = 0 - yield from op.issue([5, 2], MicrOp.OP_ADD, [0], - rdmaskn=[1, 1], + # NOP does not make any request nor response + yield from op.issue([5, 2], MicrOp.OP_NOP, [0], + rdmaskn=[1, 1], wrmask=[1], src_delays=[1, 2], dest_delays=[1]) - # note: the current test ALU down not have any masked write operations def test_compunit_fsm(): -- 2.30.2