From b19dbd13a6e89458f0ee19dad6eb199550e154a1 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 21 Mar 2019 19:58:33 +0000 Subject: [PATCH] reduce args to FPAddStage0 --- src/add/nmigen_add_experiment.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index a14ad01d..55438c2b 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -825,10 +825,10 @@ class FPAddStage0(FPState, FPID): self.mod = FPAddStage0Mod(width) self.o = self.mod.ospec() - def setup(self, m, in_a, in_b, in_mid): + def setup(self, m, i, in_mid): """ links module to inputs and outputs """ - self.mod.setup(m, in_a, in_b) + self.mod.setup(m, i) if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) -- 2.30.2