From b25bcf06665b246515186a10b954dcea24df5bf4 Mon Sep 17 00:00:00 2001 From: Raptor Engineering Development Team Date: Sat, 16 Apr 2022 13:39:41 -0500 Subject: [PATCH] Properly wire core reset to ti_rst This partially fixes Bug #812 --- src/soc/simple/issuer.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index a80941db..e41a844c 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -457,13 +457,12 @@ class TestIssuerBase(Elaboratable): comb += cd_por.clk.eq(ClockSignal()) # power-on reset delay - core_rst = ResetSignal(self.core_domain) if self.core_domain != "sync": comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal()) - comb += core_rst.eq(ti_rst) + comb += self.core_rst.eq(ti_rst) else: with m.If(delay != 0 | dbg.core_rst_o): - comb += core_rst.eq(1) + comb += self.core_rst.eq(1) with m.If(stop_delay != 0): # run DMI core-stop as well but on an extra couple of cycles comb += dbg.core_stopped_i.eq(1) -- 2.30.2