From b2f9cfbb49c48f49966d1d786c57925bad962b0f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 22 Jul 2019 09:17:39 +0100 Subject: [PATCH] whitespace --- src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py index 2c6ec33a..6cb87115 100644 --- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py +++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py @@ -71,7 +71,7 @@ class DivPipeInputData(DivPipeCoreInputData, DivPipeBaseData): def eq(self, rhs): """ Assign member signals. """ return DivPipeCoreInputData.eq(self, rhs) + \ - DivPipeBaseData.eq(self, rhs) + DivPipeBaseData.eq(self, rhs) class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData): @@ -91,7 +91,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData): """ Assign member signals. """ print (self, rhs) return DivPipeCoreInterstageData.eq(self, rhs) + \ - DivPipeBaseData.eq(self, rhs) + DivPipeBaseData.eq(self, rhs) class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData): @@ -110,7 +110,7 @@ class DivPipeOutputData(DivPipeCoreOutputData, DivPipeBaseData): def eq(self, rhs): """ Assign member signals. """ return DivPipeCoreOutputData.eq(self, rhs) + \ - DivPipeBaseData.eq(self, rhs) + DivPipeBaseData.eq(self, rhs) class DivPipeBaseStage: -- 2.30.2