From b454fb16bfe32de4af22c125247bb9ce1942a0df Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 29 Jul 2018 10:54:01 +0100 Subject: [PATCH] horrible clock-sync hack --- src/bsv/peripheral_gen/base.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index e4df4b5..e7de196 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -245,6 +245,7 @@ Ifc_sync#({0}) {1}_sync <-mksyncconnection( n_ = "{0}{1}".format(n, count) else: n_ = n + n_ = '{0}_{1}'.format(n_, pname) ret.append(template.format("Bit#(1)", n_, ck, spc)) if typ == 'in' or typ == 'inout': #fname = self.pinname_in(pname) -- 2.30.2