From b580c7703fb09fff550ba13c56368ed9b3d097e0 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 3 Jun 2021 15:42:32 +0100 Subject: [PATCH] rename ref to ref_v in PLL due to ref being a verilog keyword --- src/soc/clock/dummypll.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/clock/dummypll.py b/src/soc/clock/dummypll.py index 2363274c..1fcc4f3b 100644 --- a/src/soc/clock/dummypll.py +++ b/src/soc/clock/dummypll.py @@ -22,7 +22,7 @@ class DummyPLL(Elaboratable): clk_pll_o = Signal(reset_less=True) # output clock pll_test_o = Signal(reset_less=True) # test out pll_vco_o = Signal(reset_less=True) # analog - pll = Instance("pll", i_ref=clk_24_i, + pll = Instance("pll", i_ref_v=clk_24_i, i_a0=clk_sel_i[0], i_a1=clk_sel_i[1], o_out_v=clk_pll_o, -- 2.30.2