From b7850a7fc08e437c2a5fc3c42748851c0c8ec4f8 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 24 Mar 2021 09:26:36 +0000 Subject: [PATCH] add --disable-svp64 to litex sim build --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0ab0037e..20fe4921 100644 --- a/Makefile +++ b/Makefile @@ -24,7 +24,7 @@ develop: python3 src/soc/decoder/pseudo/pywriter.py run_sim: install - python3 src/soc/simple/issuer_verilog.py \ + python3 src/soc/simple/issuer_verilog.py --disable-svp64\ src/soc/litex/florent/libresoc/libresoc.v python3 src/soc/litex/florent/sim.py --cpu=libresoc -- 2.30.2