From b928ad938fa030928f1da4d5598bcf4709e7749a Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 24 Apr 2018 13:49:39 +0100 Subject: [PATCH] clarify --- simple_v_extension.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index b9f94b3fc..dc35f6cfa 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1047,7 +1047,7 @@ the question is asked "How can each of the proposals effectively implement a SIMD architecture where the ALU becomes responsible for the parallelism, Alt-RVP ALUs would likewise be so responsible... with *additional* (lane-based) parallelism on top. -* Thus at least some of the downsides of SIMD ISA O(N^3) proliferation by +* Thus at least some of the downsides of SIMD ISA O(N^5) proliferation by at least one dimension are avoided (architectural upgrades introducing 128-bit then 256-bit then 512-bit variants of the exact same 64-bit SIMD block) -- 2.30.2