From ba43362d4d9662676cf74c6e870eabae3601ab98 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 3 May 2023 14:28:10 -0700 Subject: [PATCH] integer mul-add is MAC not FMAC --- conferences/siliconsalon2023/siliconsalon2023.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/conferences/siliconsalon2023/siliconsalon2023.tex b/conferences/siliconsalon2023/siliconsalon2023.tex index 63cdf6f5f..09782cb13 100644 --- a/conferences/siliconsalon2023/siliconsalon2023.tex +++ b/conferences/siliconsalon2023/siliconsalon2023.tex @@ -139,10 +139,10 @@ \begin{frame}[fragile]\frametitle{Vector-Scalar Multiply} \begin{itemize} - \item Normally in FMAC the top 64-bits is thrown away. + \item Normally in MAC the top 64-bits is thrown away. \item What if we stored those 64-bits in a 2nd register?\\ (64-bit carry-out) - \item And what if the next FMAC added that "digit" on?\\ + \item And what if the next MAC added that "digit" on?\\ (64-bit carry-in) \item Again: a chain of these performs Vector-by-Scalar Multiply \end{itemize} -- 2.30.2